Datasheet

PN532_C1 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2017. All rights reserved.
Product data sheet
COMPANY PUBLIC
Rev. 3.6 — 28 November 2017
115436 17 of 222
NXP Semiconductors
PN532/C1
Near Field Communication (NFC) controller
8.1.5.2 Interrupt enable: IE0 and IE1 registers
Each interrupt source can be individually enabled or disabled by setting a bit in IE0 or IE1.
In register IE0, a global interrupt enable bit can be set to logic 0 to disable all interrupts at
once.
The 2 following tables describe IE0.
Table 10. Interrupt controller IE0 register (SFR: address A8h) bit allocation
Bit 7 6 5 4 3 2 1 0
Symbol IE0_7 IE0_6 IE0_5 IE0_4 IE0_3 IE0_2 IE0_1 IE0_0
Reset 00000000
Access R/W R/W R/W R/W R/W R/W R/W R/W
Table 11. Description of IE0 bits
Bit Symbol Description
7 IE0_7 Global interrupt enable
When set to logic 1, the interrupts can be enabled.
When set to logic 0, all the interrupts are disabled.
6 IE0_6 NFC-WI counter interrupt enable
When set to logic 1, NFC-WI interrupt is enabled. See Table 164 on page 126
.
5 IE0_5 Timer2 interrupt enable
When set to logic 1, Timer2 interrupt is enabled. See Table 36 on page 28
.
4 IE0_4 Debug UART interrupt enable
When set to logic 1, Debug UART interrupt is enabled. See Table 49 on
page 33.
3 IE0_3 Timer1 interrupt enable
When set to logic 1, Timer1 interrupt is enabled. See Table 23 on page 23
.
2 IE0_2 P33_INT1 interrupt enable
When set to logic 1, P33_INT1 pin interrupt is enabled. See Table 23 on
page 23.
The polarity of P33_INT1 can be inverted (see Table 73 on page 49
).
1 IE0_1 Timer0 interrupt enable
When set to logic 1, Timer0 interrupt is enabled. See Table 23 on page 23
.
0 IE0_0 P32_INT0 interrupt enable
When set to logic 1, P32_INT0 pin interrupt is enabled. See Table 23 on
page 23.