Datasheet

PN532_C1 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2017. All rights reserved.
Product data sheet
COMPANY PUBLIC
Rev. 3.6 — 28 November 2017
115436 167 of 222
NXP Semiconductors
PN532/C1
Near Field Communication (NFC) controller
8.6.23.28 CIU_MifNFC register (630Ch)
Defines ISO/IEC 14443A/MIFARE/NFC specific settings in target or card operating mode.
Table 228. CIU_MifNFC register (address 630Ch) bit allocation
Bit 7 6 5 4 3 2 1 0
Symbol SensMiller[2:0] TauMiller[1:0] MFHalted TxWait[1:0]
Reset 011 0 0 0 1 0
Access R/W R/W R/W R/W R/W DY R/W R/W
Table 229. Description of CIU_MifNFC bits
Bit Symbol Description
7 to 5 SensMiller[2:0] This bit defines the sensitivity of the Miller decoder.
4 to 3 TauMiller[1:0] This bit defines the time constant of the Miller decoder.
2 MFHalted Set to logic 1, this bit indicates that the CIU is set to HALT mode in
Card Operating mode at 106 kbit/s. This bit is either set by the 80C51
or by the internal state machine and indicates that only the code 52h is
accepted as a Request command.
This bit is automatically set to logic 0 by RF reset.
1 to 0 TxWait[1:0] In combination with TxBitPhase[6:0] in CIU_TxBitPhase register,
defines the additional response time for the target at 106 kbit/s in
Passive Communication mode and during the AutoColl command. See
CIU_TxBitPhase register.