Datasheet

PN532_C1 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2017. All rights reserved.
Product data sheet
COMPANY PUBLIC
Rev. 3.6 — 28 November 2017
115436 156 of 222
NXP Semiconductors
PN532/C1
Near Field Communication (NFC) controller
8.6.23.16 CIU_Coll register (EFh or 633Eh)
Defines the first bit collision detected on the RF interface.
Table 204. CIU_Coll register (address EFh or 633Eh) bit allocation
Bit 7 6 5 4 3 2 1 0
Symbol ValuesAfterColl - CollPosNotValid CollPos
Reset 1 0 1 XXXXX
Access R/W R R RRRRR
Table 205. Description of CIU_Coll bits
Bit Symbol Description
7 ValuesAfterColl If this bit is set to logic 0, all receiving bits will be cleared after a
collision.
This bit shall only be used during bitwise anticollision at 106 kbit/s,
otherwise it shall be set to logic 1.
6- Reserved
5 CollPosNotValid Set to logic 1, if no Collision is detected or the Position of the collision is
out of range of the CollPos[4:0] bits.
This bit shall only be interpreted in Passive Communication mode at
106 kbit/s or ISO/IEC 14443A/MIFARE Reader/Writer mode.
4 to 0 CollPos These bits show the bit position of the first detected collision in a
received frame, only data bits are interpreted.
Example:
00h indicates a bit collision in the 32
nd
bit.
01h indicates a bit collision in the 1
st
bit
08h indicates a bit collision in the 8
th
bit
This bit shall only be interpreted in Passive Communication mode at
106 kbit/s or ISO/IEC 14443A/MIFARE Reader/Writer mode if
CollPosNotValid is set to logic 0.