Datasheet

PN532_C1 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2017. All rights reserved.
Product data sheet
COMPANY PUBLIC
Rev. 3.6 — 28 November 2017
115436 153 of 222
NXP Semiconductors
PN532/C1
Near Field Communication (NFC) controller
8.6.23.11 CIU_FIFOData register (EAh or 6339h)
In- and output of 64 byte FIFO buffer.
8.6.23.12 CIU_FIFOLevel register (EBh or 633Ah)
Indicates the number of bytes stored in the FIFO.
Table 194. CIU_FIFOData register (address EAh or 6339h) bit allocation
Bit 7 6 5 4 3 2 1 0
Symbol FIFOData[7:0]
Reset XXXXXXXX
Access DY DY DY DY DY DY DY DY
Table 195. Description of CIU_FIFOData bits
Bit Symbol Description
7 to 0 FIFOData[7:0] Data input and output port for the internal 64 bytes FIFO buffer. The FIFO
buffer acts as parallel in/parallel out converter for all data stream in- and
outputs
Table 196. CIU_FIFOLevel register (address EBh or 633Ah) bit allocation
Bit 7 6 5 4 3 2 1 0
Symbol FlushBuffer FIFOLevel[6:0]
Reset 0 0000000
Access W RRRRRRR
Table 197. Description of CIU_FIFOLevel bits
Bit Symbol Description
7 FlushBuffer Set to logic 1, this bit clears the internal FIFO-buffer’s read- and
write-pointer and the bit BufferOvfl in the CIU_Error register immediately.
Reading this bit will always return logic 0.
6 to 0 FIFOLevel[6:0] Indicates the number of bytes stored in the FIFO buffer. Writing to the
CIU_FIFOData Register increments, reading decrements FIFOLevel.