Datasheet

PN532_C1 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2017. All rights reserved.
Product data sheet
COMPANY PUBLIC
Rev. 3.6 — 28 November 2017
115436 14 of 222
NXP Semiconductors
PN532/C1
Near Field Communication (NFC) controller
8.1.2.2 XRAM memory
The XRAM memory is divided into 2 memory spaces:
• 0000h to 5FFFh: reserved for addressing embedded RAM. For the PN532, only
accesses between 0000h and 02FF are valid.
• 6000h to 7FFFh: reserved for addressing embedded peripherals. This space is
divided into 32 regions of 256 bytes each. Addressing can be performed using R0 or
R1 and the XRAMP SFR.
The Table 6
depicts the mapping of internal peripherals into XRAM.
XRAM is accessed via the dedicated MOVX instructions. There are two access modes:
• 16-bit data pointer (DPTR): the full XRAM address space can be accessed.
• paging mechanism: the upper address byte is stored in the SFR register XRAMP; the
lower byte is stored in either R1 or R0.
The Figure 5
illustrates both mechanisms.
Table 6. Peripheral mapping into XRAM memory space
Base
Address
End
Address
Description
6000h 60FFh Reserved.
6100h 61FFh IOs and miscellaneous registers configuration
Refer to Section 8.2 “General purpose IOs configurations” on page 38
6200h 62FFh Power Clock and Reset controller
Refer to Section 8.5.7 “PCR extension registers” on page 93
6300h 633Fh Contactless Unit Interface
Refer to Section 8.6 “
Contactless Interface Unit (CIU)” on page 99
6340h FFFFh Reserved