Datasheet

PN532_C1 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2017. All rights reserved.
Product data sheet
COMPANY PUBLIC
Rev. 3.6 — 28 November 2017
115436 131 of 222
NXP Semiconductors
PN532/C1
Near Field Communication (NFC) controller
8.6.18 Interrupt request system
The CIU indicates certain events by setting interrupt bits in the register CIU_Status1 and,
in addition it will set to logic 1 CIU_IRQ_1 or CIU_IRQ_0. If this interrupt is enabled (see
Table 12 on page 18
) the 80C51 will be interrupted. This allows the implementation of
efficient interrupt-driven firmware.
8.6.18.1 Interrupt sources
The following table shows the integrated interrupt flags, the corresponding source and the
condition for its activation.
The interrupt flag TimerIRq in the register CIU_CommIrq indicates an interrupt set by the
timer unit. The setting is done when the timer decrements from logic 1 down to logic 0.
The TxIRq bit in the register CIU_CommIrq indicates that the transmitter has finished. If
the state changes from sending data to transmitting the end of frame pattern, the
transmitter unit sets automatically the interrupt bit to logic 1.
The CRC coprocessor sets the flag CRCIRq in the register CIU_DivIrq after having
processed all data from the FIFO buffer. This is indicated by the flag CRCReady set to
logic 1.
The RxIRq flag in the register CIU_CommIrq indicates an interrupt when the end of the
received data is detected.
The flag IdleIRq in the register CIU_CommIrq is set to logic 1 if a command finishes and
the content of the CIU_Command register changes to idle.
The flag HiAlertIRq in the register CIU_CommIrq is set to logic 1 if the HiAlert bit is set to
logic 1, that means the Contactless FIFO buffer has reached the level indicated by the bits
WaterLevel[5:0].
The flag LoAlertIRq in the register CIU_CommIrq is set to logic 1 if the LoAlert bit is set to
logic 1, that means the Contactless FIFO buffer has reached the level indicated by the bits
WaterLevel[5:0].
The flag RFOnIRq in the register CIU_DivIrq is set to logic 1, when the RF level detector
detects an external RF field.
The flag RFOffIRq in the register CIU_DivIrq is set to logic 1, when a present external RF
field is switched off.
The flag ErrIRq in the register CIU_CommIrq indicates an error detected by the CIU
during sending or receiving. This is indicated by any bit set to logic 1 in register CIU_Error.
The flag ModeIRq in the register CIU_DivIrq indicates that the data mode detector has
detected the current mode.
These flags are summarized with 2 interrupt bits within the register CIU_Status1:
• the high priority interrupt sources are summarized with CIU_IRQ_0.
• the low priority interrupt sources are summarized with CIU_IRQ_1.
See the register Table 190 on page 151
.