Datasheet

PN532_C1 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2017. All rights reserved.
Product data sheet
COMPANY PUBLIC
Rev. 3.6 — 28 November 2017
115436 120 of 222
NXP Semiconductors
PN532/C1
Near Field Communication (NFC) controller
8.6.11 Data mode detector
The data mode detector is able to detect received signals according to the
ISO/IEC 14443A/MIFARE, FeliCa or NFCIP-1 schemes and the standard baud rates for
106 kbit/s, 212 kbit/s and 424 kbit/s in order to prepare the internal receiver in a fast and
convenient way for further data processing.
The data mode detector can only be activated by the AutoColl command (see Section
8.6.20.12 “AutoColl command” on page 137). The mode detector is reset, when no
external RF field is detected by the RF level detector.
The data mode detector could be switched off during the Autocoll command by setting the
bit ModeDetOff in the register Mode to logic 1 (see Table 207 on page 157
).
2 cpu_need_rng Force the random number generator in running mode. When set to
logic 0, the random number generator is under control of the CIU.
When set to logic 1, the random number generator is forced to run.
1 random_dataready Indicates availability of random number. When set to logic 1, it
indicates that a new random number is available.
It is automatically set to logic 0 when the register data_rng is read.
0 - Reserved.
Table 162. Description of Control_switch_rng bits
…continued
Bit Symbol Description
Fig 38. Data mode detector
Receiver
Register settings
NFC @ 106 kbit/s / ISO/IEC 14443A
Data Mode Detector
I / Q Demodulator
CL UART
CPU access interface
sfr_rd
sfr_wr
host_rd
host_wr
Address
Data_in
Data_out
cluart_clk
cluart_reset
test_control
RX
NFC @ 212 kbit/s / FeliCa
NFC @ 424 kbit/s / FeliCa
for the detected mode
and
FIFO
Registers