Owner`s manual

however in a well-designed system these converters employ a synchronous design,

where jitter does not play any role. Of course a conversion between 96 kHz and

44.1 kHz as in the example above can be done in a synchronous manner as well.

An ASRC in fact is only required either where one or both of the sampling

frequencies involved are changing over time (

”

varispeed“ mode of digital audio

recorders) or where it is unpractical to synchronize the two sampling frequencies.

So basically in Hi-Fi jitter matters where there are A/D or D/A converters

involved. CD and DVD players are by far the most numerous type of equipment

employing D/A converters. And of course stand-alone D/A converters. Jitter,

being an analog quantity, can creep in at various places. The D/A converter

built into CD or DVD players can be

”

infected“ by jitter through various

crosstalk mechanisms, like power supply contamination by power hungry motors

(spindle/servo), microphony of the crystal generating the sampling clock or

capacitive/inductive crosstalk between clock signals etc.

In the standalone D/A converter jitter can be introduced by inferior cables

between the source (e.g. CD transport) and the D/A converter unit or by the

same mechanisms as described above — except for the motors of course. In

the case of a stand-alone D/A converter (as the DAC202), one has to take two

diﬀerent jitter contamination paths into account. One is the internal path where

internal signals can aﬀect the jitter amount of the sampling clock generator.

Here, all the good old analog design principles have to be applied. Such as

shielding from electric or magnetic ﬁelds, good grounding, good power supply

decoupling, good signal transmission between the clock generator and the actual

D/A chip.

The other path is the external signal coming from the source to which the

sampling clock has to be locked. In other words the D/A converter has to run

synchronous to the incoming digital audio signal and thus the frequency of the

internal sampling clock generator has to be controlled so that it runs at the

same sampling speed as the source (e.g. CD transport). This controlling is done

by a phase locked loop (PLL), which is a control system with error feedback.

Of course the PLL has to be able to follow the long term ﬂuctuations of the

source, e.g. the sampling rate of the source will alter slightly over time or over

temperature, it will not be a constant 44.1 kHz in the case of a CD. But the

PLL should not follow the short-term ﬂuctuations (jitter). Think of the PLL as

being like a very slow-reacting ﬂywheel.

1.2 Jitter handling in the INT203 Firewire

I/O Interface in more detail

The Jitter Elimination Technologies (JET) PLL on the chip used in the INT203

feature state-of-the art jitter rejection abilities and extremely low intrinsic jitter

levels. Like all phase-locked loops, JET PLL use feedback to lock an oscillator

to a timing reference. They track slow reference changes, but eﬀectively free-run

through rapid modulations of the reference (i.e. ﬂywheel like). From a jitter