User Documentation

Configuration

EtherCAT master and EtherCAT controller have a common area in the RAM

for data transfer. There the EtherCAT master saves the data to send and

gets the data to receive. The EtherCAT controller has (as usual for network

controller) direct access to the common RAM area (Direct Memory Access)

and transfers the data immediately to the EtherCAT bus (RAM transfer). So

a data stream between RAM and EtherCAT bus is created.

The following parameter in the area "Advanced" under "Advanced parame-

ter" have influence on the correct operation of the EtherCAT controller:

Parameter Description

DMA duration (dmaTime) Time which is available for RAM transfer

Offset of standard frame (startOffset)

Point in time where the normal process data

in the RAM are ready for collection

Offset of early frame (earlyStartOffset)

Point in time where the data for "fast control"

in the RAM are ready for collection

Fig.15-30: Timing diagram

1 ... Offset of standard frame 2 ... DMA duration

3 ... EtherCAT cycle time

The following conditions apply:

● The write operation of the EtherCAT master in the RAM buffer must be

carried out before the first read operation of the EtherCAT bus from the

RAM buffer.

● The read operation must be completed within the configured DMA dura-

tion. By default a time value of 50 µs is configured to establish the data

stream between RAM and EtherCAT bus (RAM transfer). In rare cases

some dynamic influencing factors (e.g. CPU load, RAM load, ...) can

lead to a transfer time exceeding the configured time.

Regardless of the current cycle, the following formula must be taken into ac-

count:

(Offset of standard frame + DMA duration + Frame runtime) <

EtherCAT cycle time