Specifications

Lab 5: Phase Locked Loop
Objective : To use the NE565 Phase Locked Loop (PLL) integrated circuit to demodulate
a FM signal.
Equipment :
(1) Breadboard
(1) Wavetek models 132 and 186 signal generators
(1) Tektronix P5S03 power supplies
(1) Tektronix 2445B Oscilloscope (see lab 1 for operation)
(1) Tektronix DM502A Digital Multimeter (DMM)
Components :
(1) NE565 PLL IC
(2) 680 Q resistors
(1) resistor to be determined
(2) 0.1 (if capacitors
(2) .001 uf capacitors
Parti: Free Running PLL
a) Design the PLL circuit to have a center frequency of 64 kHz. The center frequency
f
0
capture frequency f
c
and lock frequency f,, are determined by the external resistors
and capacitors chosen. The time constant is determined by the selection of capacitor C
2
.
For our purposes C
2
is . 1 uf Q: Use the following equations to determine
Lab 5 Page 1
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