Data Sheet

NEO-7 - Data Sheet
UBX-13003830 - R04 Early Production Information Electrical specification
Page 18 of 26
4.4 SPI timing diagrams
In order to avoid incorrect operation of the SPI, the user needs to comply with certain timing conditions. The
following signals need to be considered for timing constraints:
Symbol Description
SPI CS_N (SS_N) Slave select signal
SPI CLK (SCK) Slave clock signal
Table 10: Symbol description
Figure 3: SPI timing diagram
4.4.1 Timing recommendations
The recommendations below are based on a firmware running from Flash memory.
Parameter Description Recommendation
t
INIT
Initialization Time
500 µs
t
DES
Deselect Time 1 ms.
Bit rate 1 Mb/s
Table 11: SPI timing recommendations
The values in the above table result from the requirement of an error-free transmission. By allowing just a
few errors and disabling the glitch filter, the bit rate can be increased considerably.
4.5 DDC timing diagrams
The DDC interface is I
2
C Fast Mode compliant. For timing parameters consult the I
2
C standard.
The maximum bit rate is 400 kb/s. The interface stretches the clock when slowed down when serving
interrupts, so real bit rates may be slightly lower.