Datasheet

SX1302
Datasheet Rev 1.0
DS.SX1302.W.APP June 2019
22 of 31
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8.1.2 SPI Timings
All timings are given in next table for Max load cap of 10 pF.
Table 8-1: SPI Timing Requirements
Symbol Description Minimum Typical Maximum Unit
Timing constraints in SPI inputs
t
SPI,SCK
SCK period 100 ns
t
SPI,SCKH
SCK high duration 40 ns
t
SPI,SCKL
SCK low duration 40 ns
t
SPI,SCKR
SCK rise time (10% VCC_IO ->90% VCC_IO) 0 2.5 ns
t
SPI,SCKF
SCK fall time (90% VCC_IO ->10% VCC_IO) 0 2.5 ns
t
SPI,DELAY
SCK lead time 40 ns
t
SPI,QUIET
SCK trail time 40 ns
t
SPI,CSH
Time between two successive CSN chip
select
250 ns
t
SPI,CSR
CSN rise time (10% VCC_IO ->90% VCC_IO) 0 2.5 ns
t
SPI,CSF
CSN fall time (90% VCC_IO ->10% VCC_IO) 0 2.5 ns
t
SPI,SETUP
Data in setup time 5 ns
t
SPI,HOLD
Data in hold time 5 ns
SPI output timing specification
t
SPI,DOEN
SPI output enable time 0 10 ns
t
SPI,DODIS
SPI output disable time 0 10 ns
t
SPI,DOV
SCK out falling edge to MISO delay 15 ns