Datasheet

SX1302
Datasheet Rev 1.0
DS.SX1302.W.APP June 2019
21 of 31
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8. Digital Interface and Control
The transceiver is controlled via a serial interface (SPI) and a set of general purpose input/output (DIOs).
8.1 Host SPI Interface
The SPI interface gives access to the configuration register via a synchronous full-duplex frame corresponding to CPOL = 0
and CPHA = 0 in Motorola/Freescale nomenclature.
An address byte followed by a data byte is sent for a write access whereas an address byte is sent and a read byte is received
for the read access. The CSN pin goes low at the beginning of the frame and goes high after the data byte.
MOSI is generated by the master on the falling edge of SCK and is sampled by the slave (i.e. this SPI interface) on the rising
edge of SCK. MISO is generated by the slave on the falling edge of SCK.
A transfer is always started by the CSN pin going low. MISO is high impedance when CSN is high.
The host terminates an SPI transaction by raising the CSN signal, it does not explicitly send the command length as a
parameter. The host must not raise CSN within the bytes of a transaction.
8.1.1 HOST SPI Timings
Figure 8-1: SPI Timing Diagram
CSN
SCK
MOSI
MISO
t
DEL AY
t
SCK
t
SETUP
t
HOL D
t
DOV
t
DOD IS
t
QUIET
t
CSH
t
DOEN
t
SCKH
t
SCKL