Specifications

9
AT83SND2CMP3
7524D–MP3–07/07
Internal Pin Structure Table 13. Detailed Internal Pin Structure
Notes: 1. For information on resistors value, input/output levels, and drive capability, refer to
the DC Characteristics.
2. When the Two Wire controller is enabled, P
3
transistors are disabled allowing pseudo
open-drain structure.
Circuit
(1)
Type Pins
Input TST
Input/Output RST
Input/Output
P3
P4
Input/Output
P0
MCMD
MDAT
Output
ALE
SCLK
DCLK
DOUT
DSEL
MCLK
Input/Output
D+
D-
R
TST
VDD
R
RST
VSS
P
VDD
Watchdog Output
P
3
VSS
N
P
1
VDD VDD
2 osc
Latch Output
periods
P
2
VDD
VSS
N
P
VDD
VSS
N
P
VDD
D+
D-