Specifications

AT83SND2CMP3

7524D–MP3–07/07

USB Interrupt System

Interrupt System Priorities Figure 35. USB Interrupt Control System

Table 1. Priority Levels

USB Interrupt Control System As shown in Figure 36, many events can produce a USB interrupt:

• TXCMPL: Transmitted In Data. This bit is set by hardware when the Host accept a

In packet.

• RXOUTB0: Received Out Data Bank 0. This bit is set by hardware when an Out

packet is accepted by the endpoint and stored in bank 0.

• RXOUTB1: Received Out Data Bank 1 (only for Ping-pong endpoints). This bit is set

by hardware when an Out packet is accepted by the endpoint and stored in bank 1.

• RXSETUP: Received Setup. This bit is set by hardware when an SETUP packet is

accepted by the endpoint.

• STLCRC: STALLED (only for Control, Bulk and Interrupt endpoints). This bit is set

by hardware when a STALL handshake has been sent as requested by STALLRQ,

and is reset by hardware when a SETUP packet is received.

• SOFINT: Start of Frame Interrupt . This bit is set by hardware when a USB start of

frame packet has been received.

• WUPCPU: Wake-Up CPU Interrupt. This bit is set by hardware when a USB resume

is detected on the USB bus, after a SUSPEND state.

• SPINT: Suspend Interrupt. This bit is set by hardware when a USB suspend is

detected on the USB bus.

EUSB

IE1.6

IE0.7

USB

Controller

IPH/L

Interrupt Enable Lowest Priority InterruptsPriority Enable

D+

D-

IPHUSB IPLUSB USB Priority Level

0 0 0..................Lowest

0 1 1

1 0 2

1 1 3..................Highest