Specifications

44
AT83SND2CMP3
7524D–MP3–07/07
Description The USB device controller provides the hardware that the AT83SND2CMP3 needs to
interface a USB link to a data flow stored in a double port memory.
It requires a 48 MHz reference clock provided by the clock controller as detailed in Sec-
tion "", page 44. This clock is used to generate a 12 MHz Full Speed bit clock from the
received USB differential data flow and to transmit data according to full speed USB
device tolerance. Clock recovery is done by a Digital Phase Locked Loop (DPLL) block.
The Serial Interface Engine (SIE) block performs NRZI encoding and decoding, bit stuff-
ing, CRC generation and checking, and the serial-parallel data conversion.
The Universal Function Interface (UFI) controls the interface between the data flow and
the Dual Port RAM, but also the interface with the C51 core itself.
Figure 30 shows how to connect the AT83SND2CMP3 to the USB connector. D+ and D-
pins are connected through 2 termination resistors. Value of these resistors is detailed in
the section “DC Characteristics”.
Figure 28. USB Device Controller Block Diagram
Figure 29. USB Connection
USB
CLOCK
48 MHz 12 MHz
D+
D-
DPLL
SIE
UFI
USB
Buffer
To/From
C51 Core
D+
D-
R
USB
VBUS
R
USB
GND
D+
D-
VSS
To Power Supply