Specifications

35
AT83SND2CMP3
7524D–MP3–07/07
Table 36. DAC Rigth Line Out Gain Register - DAC_RLOG (06h)
Reset Value = 00000000b
Table 37. DAC Output Level Control Register - DAC_OLC (07h)
Reset Value = 00100010b
7 6 5 4 3 2 1 0
- - RLOG5 RLOG4 RLOG3 RLOG2 RLOG1 RLOG0
Bit
Number
Bit
Mnemonic
Description
7:6 - Not used
5:0 RLOG 5:0 Right channel line out digital gain selector
7 6 5 4 3 2 1 0
RSHORT ROLC2 RLOC1 RLOC0 LSHORT LOLC2 LOLC1 LOLC0
Bit
Number
Bit
Mnemonic Description
7 RSHORT
Right channel short circuit indicator (persistent; after being set, bit is not
cleared automatically even after the short circuit is eliminated; must be
cleared by reset cycle or direct register write operation)
6:4 ROLC 2:0
Right channel output level control selector
3 LSHORT
Left channel short circuit indicator (persistent; after being set, bit is not
cleared automatically even after the short circuit is eliminated; must be
cleared by reset cycle or direct register write operation)
2:0 LOLC 2:0
Left channel output level control selector