Specifications

30
AT83SND2CMP3
7524D–MP3–07/07
Note: Refer to DAC_MC register Table 38. for signal description
Master Clock and Sampling
Frequency Selection
The following table describes the different modes available for master clock and sam-
pling frequency selection by setting OVRSEL bit in DAC_CSFC register (refer to Table
39.).
Table 25. Master Clock selection
The selection of input sample size is done using the NBITS 1:0 in DAC_MISC register
(refer to Table 40.) according to Table 26.
Table 26. Input Sample Size Selection
The selection between modes is done using DINTSEL 1:0 in DAC_MISC register (refer
to Table 40.) according to Table 27.
Table 27. Format Selection
De-emphasis and dither
enable
The circuit features a de-emphasis filter for the playback channel. To enable the de-
emphasis filtering, DEEMPEN must be set to high.
Likewise, the dither option (added in the playback channel) is enabled by setting the
DITHEN signal to High.
Signal Description
LMSMIN1 Left Channel Mono/Stereo Mixer Left Mixed input enable – High to enable, Low to disable
LMSMIN2
Left Channel Mono/Stereo Mixer Right Mixed input enable – High to enable, Low to
disable
RMSMIN1
Right Channel Mono/Stereo Mixer Left Mixed input enable – High to enable, Low to
disable
RMSMIN2
Right Channel Mono/Stereo Mixer Right Mixed input enable – High to enable, Low to
disable
OVRSEL Master Clock
0 256 x FS
1 384 x FS
NBITS 1:0 Format
00 16 bits
01 18 bits
10 20 bits
DINTSEL 1:0 Format
00 I2S Justified
01 MSB Justified
1x LSB Justified