Specifications

AT83SND2CMP3

7524D–MP3–07/07

CLK. Falling edge latches AUDCDIN input and rising edge shifts AUDCDOUT output

bits.

Note that the DLCK must run during any DAC SPI interface access (read or write).

Figure 26. DAC SPI Interface Timings

Table 19. Dac SPI Interface Timings

Thsdi

Tssen

Twl

Twh

Thsen

Tssdi

AUDCDOUT

AUDCDIN

AUDCCLK

Tdsdo

Thsdo

AUDCCS

Timing parameter Description Min Max

Tc AUDCCLK min period 150 ns -

Twl AUDCCLK min pulse width low 50 ns -

Twh AUDCCLK min pulse width high 50 ns -

Tssen Setup time AUDCCS falling to AUDCCLK rising 50 ns -

Thsen Hold time AUDCCLK falling to AUDCCS rising 50 ns -

Tssdi Setup time AUDCDIN valid to AUDCCLK falling 20 ns -

Thsdi Hold time AUDCCLK falling to AUDCDIN not valid 20 ns -

Tdsdo Delay time AUDCCLK rising to AUDCDOUT valid - 20 ns

Thsdo Hold time AUDCCLK rising to AUDCDOUT not valid 0 ns -