Specifications

23
AT83SND2CMP3
7524D–MP3–07/07
Figure 21. 20 bit I2S justified mode
Figure 22. 20 bit MSB justified mode
Figure 23. 20 bit LSB justified mode
The selection between modes is done using the DINTSEL 1:0 in DAC_MISC register
(Table 40.) according with the following table:
The data interface always works in slave mode. This means that the DSEL and the
DCLK signals are provided by microcontroller audio data interface.
Serial Audio DAC Interface The serial audio DAC interface is a Synchronous Peripheral Interface (SPI) in slave
mode:
• AUDCDIN: is used to transfer data in series from the master to the slave DAC.
It is driven by the master.
• AUDCDOUT: is used to transfer data in series from the slave DAC to the master.
It is driven by the selected slave DAC.
• Serial Clock (AUDCCLK): it is used to synchronize the data transmission both in
and out the devices through the AUDCDIN and AUDCDOUT lines.
Note: Refer to Table 29. for DAC SPI Interface Description
R1 R0 L(N-1) L(N-2) L(N-3) ... L2 L1 L0 R(N-1) R(N-2) R(N-3) ... R2 R1 R0
SCLK
DSEL
DOUT
R0 L(N-1) L(N-2) L(N-3) ... L2 L1 L0 R(N-1) R(N-2) R(N-3) ... R2 R1 R0 L(N-1)
SCLK
DSEL
DOUT
R0 L(N-1) L(N-2) ... L1 L0 R(N-1) R(N-2) ... R1 R0 L(N-1)
SCLK
DSEL
DOUT
DINTSEL 1:0 Format
00 I2S Justified
01 MSB Justified
1x LSB Justified