Specifications

Integra M2106+
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WA_DEV_M2106+_PTS_003-001 April, 2007
3.6.2 Application Note with Level Shifter
A level shifter (MAX3238, for example) can be used for an application requiring V28 levels.
VCC
VCC
VCC
VCC
DCE
DTE
Wireless
CPU
®
Level Shifter
Terminal
M AX3238
ERROR
VCC
ON
Figure 11: Level shifter application diagram for serial link*
* This application note is valid for VCC ≥ 3.0 Volt (see MAX3238 specifications). Auto shutdown mode is not used in this example.
3.7 SPI Bus
The SPI bus includes a clock signal (SPI_CLK), an I/O signal (SPI_IO), and an enable signal (SPI_EN)
complying with the SPI bus standard.
Pin description
Signal Pin # I/O Reset State I/O type Description
SPI_CLK 44 O Pull up 1X SPI Serial Clock
SPI_IO 43 I/O Pull up CMOS / 1X SPI Data
SPI_EN* 42 O Output high 1X SPI Enable
* Multiplexed with GPO3.