Technical data

Table 5: Interface implementation description
GR64
variant
Application Logic
Voltage Level (V
LOGIC
)
Implementation Requirements
The application must implement level
translators to re-reference its logic level to
the logic level used by the Wireless CPU®
interface.
2.6 > V
LOGIC
> 3.0
001
2.6 < V
LOGIC
< 3.0
Connect the application logic signals directly
to the GR64001 Wireless CPU® interface.
Connect the application logic supply voltage
V
LOGIC
to VREF of the GR64002 Wireless CPU®,
and connect the application logic signals
directly to the Wireless CPU® interface.
002 1.8 ≤ V
LOGIC
≤ 5.0
4.6.1 VREF as an Output from the Wireless CPU®
The GR64001 variants provide a 2.8V VREF reference output to the host side level
translator devices. This enables legacy users, and users of older interface technology
to connect directly to the GR64’s IO. In this arrangement VREF can be used as a
further level translator reference in the users application circuits, or to power external
circuits, since it has a 75mA current sourcing capability.
Parameter Min Nom Max Unit
VREF output voltage 2.74 2.8 2.86 V
VREF load current 75 mA
!
WARNING
Note that at power down, this VREF pin will go high impedance. To
ensure a low level after power down, implement a pull-down resistor.
The value of the resistor depends on the application implementation.
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GR64 Integrators’ Manual
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