Technical data

4.3.1.2 I2C Level Translator Interface
Because of the nature of the I2C interface signals, SDA (data) & SCL (clock), they
utilize a different type of level-translating technology to that of the ‘common’ IO.
The I2C level translator IC uses an open drain construction with no direction pin,
ideally suited to bi-directional low voltage (such as the GR64 1.8 V processor) I2C
port translation to the normal 3.3 V or 5.0 V I2C-bus signal levels. Unlike the
common level translators, the I2C level translators have a very low (6.5ohm RDSON)
resistance between input and output pins.
The I2C level translators use VREF as the host-side voltage reference and the internal
1.8V digital IO core as the Wireless CPU®-side reference.
4.4 Grounds
Pin Name Direction Function
2 GND - Ground
4 GND - Ground
6 GND - Ground
8 GND - Ground
10 GND - Ground
12 GND - Ground
60 AREF - Analogue reference
There are two ground connections in the Wireless CPU®, AREF (analogue ground) and
GND (digital ground). Pin assignments are shown in the table above.
AREF and GND are connected at a single point inside the Wireless
CPU®; however they must not be joined together in the user
application.
NOTE
This document is the sole and exclusive property of WAVECOM. Not to be distributed or divulged without prior written agreement.
Ce document est la propriété exclusive de WAVECOM. Il ne peut être communiqué ou divulgué à des tiers sans son autorisation préalable
GR64 Integrators’ Manual
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