INTEGRATORS’ MANUAL GR64 GSM/GPRS Wireless CPU® Reference: WI_DEV_GR64_UGD_001 Version: 002 Date: 2007/02/06
Trademarks ®, WAVECOM®, WISMO®, Open AT®, Wireless CPU®, Wireless Microprocessor® and certain other trademarks and logos appearing on this document, are filed or registered trademarks of Wavecom S.A. in France or in other countries. All other company and/or product names mentioned may be filed or registered trademarks of their respective owners. Copyright This manual is copyrighted by WAVECOM with all rights reserved.
Revision History Edition Change Information First First Edition Updated FCC marking requirements Second Signal connectivity table updated Modified description of UART1 signal behaviour Third Review comment implementations Fourth Implemented review comments, “Wireless CPU®®” registered signs GR64 Integrators’ Manual Page: 3/106 This document is the sole and exclusive property of WAVECOM. Not to be distributed or divulged without prior written agreement.
Contents 1 Introduction .......................................................................................... 10 1.1 TARGET USERS........................................................................................................ 10 1.2 PREREQUISITES ....................................................................................................... 10 1.3 MANUAL STRUCTURE .............................................................................................. 10 1.4 NOTATION ....
2.6.4 2.7 3 DISPOSAL OF OLD ELECTRONIC EQUIPMENT .................................................... 24 PRODUCT MARKING................................................................................................ 24 Mechanical Description ......................................................................... 26 3.1 INTERFACE DESCRIPTION ........................................................................................ 26 3.2 ANTENNA PAD...................................................
4.9.4 SPEAKER SIGNALS (EARP, EARN) ....................................................................... 57 4.10 PCM DIGITAL AUDIO (SSP) ................................................................................... 58 4.11 SERIAL DATA INTERFACES ................................................................................... 61 4.10.1 4.11.1 PCM DATA FORMAT ........................................................................................ 59 UART1 ..................................
6.2 SIM CARD ............................................................................................................... 86 6.3 ANTENNA ............................................................................................................... 86 6.4 INSTALLATION OF THE WIRELESS CPU® ................................................................... 87 6.4.1 WHERE TO INSTALL THE WIRELESS CPU® .......................................................... 87 6.4.1.1 Environmental Conditions....
9.5 ENVIRONMENTAL SPECIFICATION ............................................................................ 97 10 Regulatory Notices .............................................................................. 100 11 Introduction to the Universal Developer’s Kit ...................................... 105 GR64 Integrators’ Manual Page: 8/106 This document is the sole and exclusive property of WAVECOM. Not to be distributed or divulged without prior written agreement.
Table of Figures Figure 1: Main Blocks in a Wireless System (embedded application) .................................... 15 Figure 2: Main Blocks in a Wireless System (external micro-controller) ............................... 16 Figure 3: Wireless CPU® viewed from below ....................................................................... 26 Figure 4: Wireless CPU®, viewed from above (Integrated SIM holder variant) ....................... 26 Figure 5: Antenna pig-tail pads ................................
1 Introduction 1.1 Target Users The GR64 Wireless CPU®s are designed to be integrated into machine-to-machine or man-to-machine communications applications. They are intended to be used by manufacturers, system integrators, applications developers and developers of wireless communications equipment. 1.2 Prerequisites It is assumed that the person integrating the Wireless CPU® into an application has a basic understanding of the following: 1.
1.4 Notation The following symbols and admonition notation are used to draw the reader’s attention to notable or crucially-important information.
1.
Abbreviation ME MMCX Mobile Equipment (Wireless CPU® without SIM card) Micro Miniature Coax MO Mobile Originated MS Mobile Station (Wireless CPU® with SIM card) MT Mobile Terminated PCM 1.
2 GR64 Wireless CPU® 2.1 About the GR64 The Wavecom Gx64 family of devices are Quad Band GSM/GPRS Wireless CPU®s operating in the GSM 850/900/1800/1900 bands. These products belong to a new generation of Wavecom Wireless CPU®s, and are intended to be used in machine-to-machine applications and man-to-machine applications. They are used when there is a need to send and receive data (by SMS, CSD, or GPRS), and make voice calls over the GSM network.
2.2 Wireless CPU® in a Communication System Figure 1 and Figure 2 illustrate the main blocks of a wireless communication system using the Wireless CPU®. Figure 1 shows the communication system when the script is embedded on the Wireless CPU® and Figure 2 shows the communication system when a micro-controller is used. They also show the communication principles of the system and the interface between the Wireless CPU® and the application.
MS GR64 SIM GSM NETWORK SIM STATUS & RESPONSE SYSTEM INTERFACE DC POWER DTE DTE GSM GSM ENGINE ENGINE DCE DCE COMMAND & CONTROL Figure 2: Main Blocks in a Wireless System (external micro-controller) In accordance with the recommendations of ITU-T (International Telecommunication Union - Telecommunications Standardization Sector) V.24, the TE communicates with the MS over a serial interface.
2.3 Features The Wireless CPU® performs a set of telecom services (TS) according to 3GPP release 99 and ITU-T. The functions of the Wireless CPU® are implemented by issuing AT commands over a serial interface. 2.3.1 Types of Wireless CPU® Equipment The GR64 is a fully Quad Band capable GSM/GPRS Wireless CPU® with the characteristics shown in the table below.
• CBM (cell broadcast message); a service in which a message is sent to all subscribers located in one or more specific cells in the GSM network (for example, traffic reports) • SMS status report according to 3GPP TS 23.40 The maximum length of a text mode SMS message is 160 characters using 7-bit encoding. The Wireless CPU® supports up to six concatenated messages to extend this function. Concatenation is performed by the host application. 2.3.
2.3.5 GPRS Multi-Slot Support GSM Multi-slot classes supported by Gx64 devices Multi-slot Class 8 Maximum slot allocation Downlink Uplink Active 4 1 5 Allowable 1 up; 4 down 1 up; 4 down 10 4 2 5 2 up; 3 down 2.3.6 Max data rate Configuration 8-12Kbps Send 32-48Kbps Receive 8-12Kbps Send 32-48Kbps Receive 16-24Kbps Send 24-36Kbps Receive SIM Card The GR64 supports an external SIM card through its system connector. A variant of the GR64 also supports an on-card SIM.
The power consumption figures shown represent typical average current for maximum transmitted power, single uplink (transmit) slot, and single downlink (receive) slot. The Wireless CPU® will consume more average power in different multi-slot configurations, the worst case being that of two uplink and three downlink slots. 2.3.
2.4 Service and Support 2.4.1 Web Pages Visit the Wavecom extranet web site for the following information: • Where to buy Wireless CPU®s or for recommendations concerning accessories and components • Local contact details for customer support in the region • FAQs (frequently asked questions) Access to the Wavecom extranet site requires a user account and password. Accounts can be arranged through the local account manager. The extranet web site address is: http://www.wavecom.
Make sure to order the M2M Wireless CPU®(s) that are applicable to the needs of the organization. Also, ensure that the integrator have computer or micro-controller. The AT command manual provides the necessary command and control reference to drive the Wireless CPU®. 2.5 Precautions The Wireless CPU®s are ESD protected up to ±15kV on all 2.8V IO pins. All other pins are protected up to ±2kV.
2.6.2 Radio Frequency (RF) Exposure and SAR The Wireless CPU® device is a low-power radio transmitter and receiver (transceiver). When it is turned on, it emits low levels of radio frequency energy (also known as radio waves or radio frequency fields). Governments around the world have adopted comprehensive international safety guidelines, developed by scientific organizations, e.g.
2.6.4 Disposal of Old Electronic Equipment This symbol on the product or on its packaging indicates that this product shall not be treated as household waste. Instead it shall be handed over to an appropriate collection point for the recycling of electrical and electronic equipment.
INTEGRATING THE WIRELESS CPU® GR64 Integrators’ Manual Page: 25/106 This document is the sole and exclusive property of WAVECOM. Not to be distributed or divulged without prior written agreement. Ce document est la propriété exclusive de WAVECOM.
3 Mechanical Description 3.1 Interface Description The pictures below show the mechanical design of the Wireless CPU® along with the positions of the different connectors and mounting holes. The Wireless CPU® is protected with tin coated steel ASI 1008/1010 covers that meet the environmental and EMC requirements.
Please note the following: • Mounting holes positioned at the corners make it possible to securely bolt the Wireless CPU® into the application. • Keypad, display, microphone, speaker and battery are not part of the Wireless CPU®. • For the GR64 variant without an integrated SIM holder, the SIM card is mounted in the user application, external to the Wireless CPU® (this is also an option for the integrated SIM holder variant). • The System Connector is a 60-pin standard 0.05 in (1.27 mm) pitch type.
3.3 Physical Dimensions Figure 6: Dimensions of the Wireless CPU® (Integrated SIM variant) GR64 Integrators’ Manual Page: 28/106 This document is the sole and exclusive property of WAVECOM. Not to be distributed or divulged without prior written agreement. Ce document est la propriété exclusive de WAVECOM.
Figure 7: Dimensions of the Wireless CPU® (Legacy variant) Measurements are given in millimetres. See also Technical Data, in Section 9. GR64 Integrators’ Manual Page: 29/106 This document is the sole and exclusive property of WAVECOM. Not to be distributed or divulged without prior written agreement. Ce document est la propriété exclusive de WAVECOM.
4 System Connector Interface 4.1 Overview Electrical connections to the Wireless CPU® (except the antenna), are made through the System Connector Interface. The system connector is a 60-pin, standard 0.05 in (1.27 mm) pitch device. The system connector allows both board-to-board and board-to-cable connections to be made. Use a board-board connector to connect the Wireless CPU® directly to a PCB, and a board-cable connector to connect the radio device via a cable.
Table 2: Pin Assignments PIN Pin Name Direction Function 1 VCC Input DC power Yes 2 GND - Ground Yes 3 VCC Input DC power Yes 4 GND - Ground Yes 5 VCC Input DC power Yes 6 GND - Ground Yes 7 VCC Input DC power Yes 8 GND - Ground Yes 9 VCC Input DC power Yes 10 GND - Ground Yes 11 CHG_IN Input 12 GND - ADIN4 Input GPIO5 In/Out 14 ON/OFF Input 15 SIMVCC Output 16 SIMDET Input 17 SIMRST 18 13 Req Battery charger power Ground Yes A
Name Direction 35 TX_ON Output Transmit indication RI Output Ring Indicator GPIO8 In/Out General purpose IO DTR1 Input GPIO10 In/Out General purpose IO DCD1 Output Data Carrier Detect (UART1) GPIO11 In/Out General purpose IO RTS1 Input GPIO9 In/Out General purpose IO CTS1 Output Clear To Send (UART1) GPIO12 In/Out General purpose IO 41 DTM1 Input Data To Wireless CPU® from host (UART1) Yes3 42 DFM1 Output Data From Wireless CPU® to host (UART1) Yes3 43 DTM3 Inpu
4.2 Dealing with Unused Pins Integrators applications may connect all of the GR64 signals pins, or just those necessary for minimal operation, or most commonly some other permutation. If GR64 signal pins are not connected to the host application the integrator should terminate them in the following manner.
Pin Name Unused pin termination 37 DTR1/GPIO10 Leave Open 38 DCD1/GPIO11 Leave Open 39 RTS1/GPIO9 Leave Open 40 CTS1/GPIO12 Leave Open 41 DTM1 Leave Open 42 DFM1 Leave Open 43 DTM3 Leave Open 44 DFM3 Leave Open 45 USBDP Leave Open 46 USBDN Leave Open 47 SSPDTM Leave Open 48 SSPDFM Leave Open 49 VUSB Leave Open 50 ALARM Leave Open 51 SSPFS Leave Open 52 SSPCLK Leave Open 53 MICIP Connect to AREF 54 MICIN Connect to AREF 55 EARP Leave Open 56 EARN
4.3 General Electrical and Logical Characteristics The core digital IO is based upon 1.8V technology in the Baseband chipset. All external IO signals undergo bi-directional level shifting on the physical Wireless CPU® to provide flexibility to users of different voltage technology. An internal core IO regulator is used as a reference for the Wireless CPU®-side logic, whilst the application (host-side) reference is fed by VREF in one of two implementations.
4.3.1 Level Translator Interfaces Two different level translator circuits are implemented in GR64. The ‘common’ interface is used on all level-translated IO with the exception of the I2C signals, SDA & SCL. 4.3.1.1 Common Level Translator Interface The common level translator used within the GR64 uses a Maxim MAX3001E. The level translators have built-in ESD protection to ±15kV (HBM).
4.3.1.2 I2C Level Translator Interface Because of the nature of the I2C interface signals, SDA (data) & SCL (clock), they utilize a different type of level-translating technology to that of the ‘common’ IO. The I2C level translator IC uses an open drain construction with no direction pin, ideally suited to bi-directional low voltage (such as the GR64 1.8 V processor) I2C port translation to the normal 3.3 V or 5.0 V I2C-bus signal levels.
4.4.1 Analogue Ground (AREF) AREF is the return signal, or analogue audio reference, for AUXI and AUXO. These two signals provide a single-ended auxiliary audio input (host to Wireless CPU®) and output (Wireless CPU® to host). AREF is connected to the common GND inside the Wireless CPU® only. The application must not connect GND and AREF. AREF is to be used as a reference signal for the application AUXI and AUXO amplifiers (see figure below). Figure 10: AREF implementation example for AUXI and AUXO 4.
4.5 Regulated Power Supply Input (VCC) Pin Name Direction Function 1 VCC Input DC power 3 VCC Input DC power 5 VCC Input DC power 7 VCC Input DC power 9 VCC Input DC power Power is supplied to the Wireless CPU® VCC pins, from an external source. User application circuitry should connect all VCC pins together in to carry the current drawn by the Wireless CPU®. The electrical characteristics for VCC are shown in the following table.
The Wireless CPU® has approximately 40μF of internal capacitance across the VCC pins. During initial power-up the host power supply CAUTION will have to charge this capacitance to the operating voltage. This initial in-rush current may exceed the Wireless CPU®’s normal peak current, sometimes greater than an order of magnitude higher (depending upon the power supply design) for a short duration (generally a few microseconds).
4.6 Voltage Reference (VREF) Pin Name Direction 34 VREF Input (Output) Function Core voltage reference GR64 provides a voltage reference interface for user applications. Level translators are integrated in the GR64 product. The integrated level translators are referenced to an internal IO regulator on the Wireless CPU® side and to an application voltage on the user side of the interface (VREF).
Table 5: Interface implementation description GR64 variant Application Logic Voltage Level (VLOGIC) Implementation Requirements The application must implement level 2.6 > VLOGIC > 3.0 001 translators to re-reference its logic level to the logic level used by the Wireless CPU® interface. 2.6 < VLOGIC < 3.0 Connect the application logic signals directly to the GR64001 Wireless CPU® interface. Connect the application logic supply voltage 002 1.8 ≤ VLOGIC ≤ 5.
4.6.2 VREF as an Input to the Wireless CPU® The GR64002 variants provide VREF as a reference input for the host side logic. This enables users of varying technologies to connect directly to the GR64’s IO by providing a reference voltage from their own application IO. The application must apply their logic reference voltage on VREF and then connect their logic I/O’s directly to GR64. This eliminates the need for level translators in the application. Parameter Min VREF input voltage 1.
Figure 12: GR64 Charger Implementation The GR64 Wireless CPU® supports only one mode of charging, microprocessor supervised pulsed-charging. Also, the Wireless CPU® only supports one battery cell type as standard. Battery charging algorithms are unique to different battery types. Wavecom will not accept any responsibility or liability for damage, DANGER product failures, even death or injury occurring as a result of incompatible battery and charging algorithms being applied.
During microprocessor supervised mode, the GR64 takes a current-limited voltage source at the CHG_IN pin to implement constant-current charging of a single Li-Ion cell connected to the VCC pins. Figure 13: Typical application for pulse charging a battery 4.7.1 Charging Process Figure 13 shows a typical battery charging implementation. The voltage source must be current limited (500 mA max). A reverse current protection diode prevents external fault conditions from draining the battery.
level if it subsequently falls below VCC by 50 mV. If the relative voltage of CHG_IN goes invalid and remains invalid for the duration of the detection delay, charging is terminated. As a safety precaution, the battery cell voltage must be at least 2.5 V before fastcharge is allowed to take place. If the battery cell voltage is less than 2.5 V, it is considered either deeply discharged or shorted. To protect a Li-ion cell from the damage that may occur if it is fast-charged from this state, a 3.
The lithium ion battery is free from the so-called memory effect, a phenomenon associated with nickel cadmium in which the apparent battery capacity decreases when shallow charge and discharge cycles are repeated. A single lithium ion cell has a voltage of 3.7V (mean value), which is equal to either three nickel cadmium or nickel-metal hydride cells connected in series. This voltage is close to the nominal VCC of the GR64 device.
• monitor battery temperature during charging using a thermistor placed on or near the battery wired to an ADC input on the Wireless CPU® Li-Ion batteries have a higher ESR (compared to Ni-Cd or Ni-MH), although this should not be a limiting factor for peak current delivery, any battery should be capable of at least 50% greater than the GR64 demands (~3A peak) To determine battery life, on a full charge, the following rule of thumb can be applied: • Standby time = Battery Capacity (mAh) / Idle current
4.8 Powering the Wireless CPU® ON and OFF (ON/OFF) Pin Name Direction Function 14 ON/OFF Input Device on/off control The ON/OFF description below references a GR64001 Wireless CPU® variant. The timing is also valid for the GR64002 variant with the exception that VREF can be excluded since it is input to the Wireless CPU® by the application. VREF shall in the GR64002 variant implementation be seen as the Wireless CPU®’s internal logical voltage supply. 4.8.
Initially, power is supplied to the VCC pins. The presence of power raises the ON/OFF through a pull-up resistor to VCC potential. In order to power the Wireless CPU®, ON/OFF is pulled to ground. Once ON/OFF has been held low for 125ms (denoted by t1) the primary LDOs power up; the VREF signal comes from one of the primary LDOs. For Wireless CPU® variants where VREF supplies a reference voltage to the host, it acts as a useful indicator that the Baseband is powered.
4.8.2 Turning the Wireless CPU® Off Figure 15: Power Off timing for GR64001 ! WARNING Failure to implement the proper shut down procedure could result in permanent damage to the device including, but not limited to, erasure of critical parameters stored in non-volatile memory. Product warranty is invalidated in such circumstances. Powering the GR64 power down sequence is shown above. The significant signals are VCC, ON/OFF and VREF, shown by solid lines.
The RTC can continue to operate even though VCC is removed, provided that a sufficiently charged backup device is connected to the VRTC. Refer to section 4.20 for details. NOTE The relevant characteristics of the ON/OFF Power control interface are shown in the table below. Parameter Input current GR64 Integrators’ Manual Page: 52/106 Conditions Min Typ Max Unit Input low (0V), VCC = 3.6V -60 -25 -12 μA 1 μA Input high (VCC), VCC = 3.
Analogue Audio High-level Low-level 4.
4.9.1 Auxiliary Audio to Wireless CPU® (AUXI) AUXI is a single-ended auxiliary analogue audio input to the Wireless CPU®. Internally, the signal is routed to the CODEC (Coder/DECoder), where it is converted to digital audio and mapped to an internal bus. Figure 16: Auxiliary input connections to the Wireless CPU® The AUXI input is a passive network applying -5dB of gain followed by the transmit part of the CODEC.
4.9.2 Auxiliary Audio from Wireless CPU® (AUXO) AUXO is a single-ended auxiliary analogue audio output from the Wireless CPU® and may be used to drive a speaker or an earpiece. The interface has an internal 100nF coupling capacitor; a load of 10kohm will provide a near full-scale output capability between 300 to 4300 Hz. Figure 17: Auxiliary output connections to the Wireless CPU® The table below shows the audio signal levels for AUXO.
4.9.3 Microphone Signals (MICIP, MICIN) MICIP and MICIN are balanced differential microphone input pins. These inputs are compatible with an electret microphone. The microphone contains a FET buffer with an open drain output, which is supplied with at 2.4V ±10% relative to ground by the Wireless CPU® as shown below. Figure 18: Microphone input connections to the Wireless CPU® The input low-noise amplifier stage is constructed out of standard low-noise op amps.
4.9.4 Speaker Signals (EARP, EARN) EARP and EARN are the speaker output signals. These are differential-mode outputs. With a full-scale PCM input to the CODEC, 0 dB audio output gain setting, and a differential load RL = 30 ohm, the output voltage between EARP and EARN is 1.5 V rms. For load resistances less than 30 ohm, the full-scale output needs is limited using the Wireless CPU®’s internal programmable gain attenuator.
4.10 PCM Digital Audio (SSP) Pin Name Direction Function 48 SSPDFM Output Serial PCM data from Wireless CPU® to host 47 SSPDTM Input Serial PCM data to Wireless CPU® from host 51 SSPFS In/Out Serial PCM frame synchronisation 52 SSPCLK In/Out Serial PCM clock The SSP (Synchronous Serial Port) digital interface is configured to provide a PCM (digital) audio interface.
4.10.1 PCM Data Format The PCM digital audio interface for GR64 is based upon the Texas Instruments SSI standard. The SSP interface can be programmed for data frame sizes between 4 to 16 bits. The clock rate is fixed to 128kHz. PCMCLK (bit clock) and PCMSYNC (frame synchronization) are both generated by the DSP within the Wireless CPU®. The DSP within the Wireless CPU® in this instance is the master for all external PCM, so clocks and data from external devices must be synchronized to it.
SSPCLK SSPFS SSPDTM LSB MSB LSB MSB SSPDFM LSB MSB LSB MSB Frame n-1 Frame n Frame n+1 Figure 23: PCM Frame format for a continuous transfer GR64 Integrators’ Manual Page: 60/106 This document is the sole and exclusive property of WAVECOM. Not to be distributed or divulged without prior written agreement. Ce document est la propriété exclusive de WAVECOM.
4.11 Serial Data Interfaces The serial channels consist of two UARTs and a USB port. communication links to the application or accessory units. These provide The serial channels can be used in differing configurations, depending upon the user’s requirements and application. However, the common configuration options are described: • UART1 has full RS-232 functionality and is used for all on- and off –line communication (modem sleep & wake functional control is an integral component of this interface).
UART1 is a full featured Universal Asynchronous Receiver Transmitter providing fullduplex asynchronous communication. UART1 has the following features: • 32 bytes of FIFO for both receive and transmit • FIFO threshold interrupts • 1 start bit, 7 or 8 data bits, 1 optional parity bit, 1 or 2 stop bits • Programmable baud rate • Auto-configuration mode with auto-baud and auto-format operation • Hardware flow control • Software flow control.
4.11.1.1 Serial Data Signals (DTM1, DFM1) The default baud rate of the UARTs is auto-baud. Baud rates of between 600 bauds to 460k bauds are possible. The Wireless CPU® also supports 3GPP TS 27.010 multiplexing protocol, which starts when the appropriate command is sent. 4.11.1.1.1 Serial Data From Wireless CPU® (DFM1) DFM1 is an output signal that the Wireless CPU® uses to send data via UART1 to the host application. 4.11.1.1.
4.11.1.3 Control Signals (DTR1, DSR1, DCD1, RI) 4.11.1.3.1 Data Terminal Ready (DTR1) DTR indicates that the DTE is ready to receive data. It also acts as hardware ‘hang- up’, terminating calls when switched high. The signal is active low. Users can define the exact behaviour of DTR with the AT&D command. DTR1 is used as an optional sleep control mechanism when the Wireless CPU® is configured appropriately. 4.11.1.3.2 Data Set Ready (DSR1) DSR indicates that the DCE is ready to receive data.
4.11.2 UART3 (DTM3, DFM3) The reason UART2 is skipped is that GR64 does not support more than two UART interfaces. The removed interface was represented by UART2 for the GR47/48, so for legacy reasons the second UART in GR64 is called UART3. Pin Name Direction Function 43 DTM3 Input Data To Wireless CPU® from host (UART3) 44 DFM3 Output Data From Wireless CPU® to host (UART3) UART 3 consists of a full duplex serial communication port with transmission and reception lines.
4.11.3 USB Pin Name Direction Function 45 USBDP In/Out USB data positive 46 USBDN In/Out USB data negative 49 VUSB Input USB DC power The USB interface is compliant with the USB2.0 standard for a full speed (12Mbps) endpoint device. Together with VUSB and GND it creates a standard USB 4-pin interface. VUSB (VBUS in the USB standard) is nominally 5.0V. Parameter Conditions VUSB Input voltage level IVUSB Current consumption (VUSB=5.0V) Limit Unit Min Typ Max 4.5 5.0 5.
• Firmware ability to wake up and reset a suspended device • 8, 16, 32, and 64-byte FIFO sizes for non-isochronous transfers • 64, 256, 512, and 1024-byte FIFO sizes for isochronous transfers • Trace debug port for Wireless CPU® diagnostics The USB interface supports 3GPP TS 27.010 multiplexing, and may be used as the primary AT-command interface. Internally, the USBDP line is pulled up by a 1.
This SIM interface allows the use of 3 V and 1.8 V SIM cards (5V is unsupported). The Wireless CPU® automatically detects the SIM type, switching the signal voltages accordingly. Signal Parameter SIMVCC SIM supply voltage Mode Min Typ Max Unit 1.8 1.71 1.8 1.89 V 3.0 2.75 2.9 3.05 V Short circuit current Quiescent Supply Current 10 3.0 Output Capacitance SIMCLK / SIMRST SIMDAT Output Capacitor ESR mA 20 μA 0.3 2.0 μF 0.01 1.0 ohm High level input 1.8 0.
4.12.1 SIM Detection (SIMDET) SIMDET is used to determine whether a SIM card has been inserted into or removed from the SIM card holder. The integrator should normally wire it to the ‘card inserted switch’ of the SIM card holder, but different implementations are possible. An internal pull-up resistor keeps the SIMDET-signal at a high level (1.8V) when left open. This means ‘SIM card missing’ to the Wireless CPU®. When pulled low the radio device assumes a SIM card is inserted.
4.13 Service/Programming Pin Name Direction 58 SERVICE Input Function Flash programming enable signal The SERVICE interface is flash programming enable input. The SERVICE pin is driven active high by the host application using either a logic control input or applying a dc voltage (common in legacy applications) to begin a flash download. This pin should be pulled low or grounded during normal use. The SERVICE signal drives an N-channel FET switch which has a resistive divider on the input.
The application must have the capability to set this signal active high. The signal is not needed to perform normal SW-updating through “Updater”, but it is needed to support special service tools from CAUTION Wavecom. The SW updating tool for GR64 is “Updater”. The Updater is a local application that downloads a signed image provided by Wavecom. It is not necessary to set SERV active to run “Updater”. NOTE 4.
4.15 LED Pin Name Direction 33 LED Output Function LED control signal The LED interface is intended to operate a status LED, which can be programmed on and off, or for a particular blink sequence. The LED signal is derived from a standard GPIO and does not have sufficient drive capability to operate an LED directly, so it requires the user to implement some form of transistor circuit. implementation is shown below.
4.
• Polarity (inversion) • Internal pull-up resistors The internal pull-up resistors are applied on the Wireless CPU® side of the level translators. If the application is using a GPIO as an input and need a pull-up resistor, the application must provide that externally. CAUTION To overcome the 6k input impedance of the level translator, the pullup resistor must be in the 680 ohm range. This could potentially increase current consumption, so it is recommended to use CMOSlogic (see 4.3.1.
4.16.2 LED/IO6 Capabilities The LED function pin can be used as a general purpose digital I/O when the flashing LED function is not required. However, this pin does not have an on-board pull-up resistor. It is required that an external pull-up or pull-down resistor be provided by the host circuitry when either not used or when used as a digital input. 4.16.3 ADIN4 A further ADC input (in addition to the three dedicated pins) is created by multiplexing one of the GPIO signals (GPIO5). 4.
Figure 27: ADC sharing arrangement ADC sampling frequency and sampling source selection can be set up and controlled with AT-commands by the user. ADC samples requires up to 5 clock (ADCLK) cycles to process. The ADC also performs some system-level sampling. These two factors limit the maximum practical sampling rate to around 20ksps.
High-level Input Voltage ADC Clock (ADCLK) ADC Conversion Time ADC Sample Delay GR64 Integrators’ Manual Page: 77/106 ADC output=3FFh 2.45 260 325 2.59 V 390 kHz 12 ADCLK 5 ADCLK This document is the sole and exclusive property of WAVECOM. Not to be distributed or divulged without prior written agreement. Ce document est la propriété exclusive de WAVECOM.
4.18 I2C Serial Control Bus Pin Name Direction Function 29 SDA In/Out I2C data 30 SCL Output I2C clock The I2C interface comprises two signals; data (SDA) and clock (SCL). Both SDA and SCL have pull-up resistors. Therefore, when the bus is free, both SDA and SCL are in a HIGH state. The GR64 implementation of I2C supports only a single master mode, with the Wireless CPU® being the master.
Fast-mode signal characteristics Parameter Min SCL clock frequency Typ 0 Max Unit 400 kHz LOW period of the SCL clock 1.3 μs HIGH period of the SCL clock 0.6 μs Data hold time 0.9 μs 400 pF 0 Capacitive load for each bus line 4.19 Burst Transmission (TX_ON) Pin Name Direction 35 TX_ON Output Function Transmit indication Burst transmission is the period during which the GSM transceiver is transmitting RF signals. TX_ON is an indicator that the Wireless CPU® is transmitting.
Figure 28: Recommended circuitry for a TX_ON implementation 4.20 Real Time Clock The real-time clock (RTC) is driven by a 32.768 kHz clock from an internal crystal oscillator. The clock is divided by 32,768 to generate a clock with a 1 second period that increments a 29-bit seconds counter. In addition, it can generate interrupts at a programmed time. The following are the features of RTC: • 17-year time interval with 1 second resolution.
4.20.1 Real Time Clock Backup Supply (VRTC) Pin Name Direction Function 25 VRTC Input DC supply for real time clock VRTC provides an input connection to the Wireless CPU® which allows the user to power the real time clock (RTC) within the GR64 by way of a coin cell or charged capacitor. When the Wireless CPU® is powered, an internal LDO regulator provides a 200 A source designed to supply the microprocessor’s RTC block.
In the backup condition the RTC block will function to as low as 1.1V on the VRTC pin. The RTC draws 10µA typically during powered backup (15µA max). Figure 29 shows the VRTC connectivity arrangement. Figure 29: VRTC connection Recommended button cell to use is Seiko TS414H. This is a lead-free, reflowable SMT Lithium battery with a nominal voltage of 1.5V. TIP GR64 Integrators’ Manual Page: 82/106 This document is the sole and exclusive property of WAVECOM.
4.20.2 RTC Alarm (ALARM) Pin Name 50 ALARM Direction Output Function RTC Alarm The ALARM signal is only available on GR64002. NOTE The Alarm output is logic output from the Wireless CPU® which is supplied from the RTC circuitry block. This block is, in turn, supplied either from the main supply of the Wireless CPU® or from a backup battery if the main supply is not available. This signal is pulled up inside the Wireless CPU® to VRTC and is set low for 1s when an Alarm is triggered.
5 Antenna Connector The Wireless CPU®’s antenna connector allows transmission of the radio frequency (RF) signals from the Wireless CPU® to an external customer supplied antenna. The connector is a micro-miniature coaxial MMCX through hole-mounted socket. A number of suitable MMCX type, mating plugs are available from the following manufacturers: • Amphenol • Suhner • IMS Connector Systems The nominal impedance of the antenna interface is 50 ohms.
6 Hints for Integrating the Wireless CPU® This chapter gives the integrator advice and helpful hints on how to integrate the Wireless CPU® into the application from a hardware perspective. Make sure the integrator read and consider the information under the following headings before starting the integration work: 6.1 6.1.1 • Safety advice and precautions • Installation of the Wireless CPU® • Antenna Safety Advice and Precautions General Always ensure that use of the Wireless CPU® is permitted.
6.2 SIM Card Before handling any SIM card, users should ensure that they are not charged with static electricity. Use proper precautions to avoid electrostatic discharges. The Wireless CPU® must be switched off before the SIM card is installed or uninstalled. When the SIM card holder is opened, the SIM card connections lie exposed under the SIM card holder.
6.4 Installation of the Wireless CPU® 6.4.1 Where to Install the Wireless CPU® The following conditions need to be taken into consideration when designing the application as they might affect the Wireless CPU® and its function: • Environmental conditions • Signal strength • Connection of components to Wireless CPU® • Network and subscription 6.4.1.
6.4.1.3 Connection of Components to Wireless CPU® The integrator is responsible for the final integrated system. Incorrectly designed or installed, external components may cause radiation limits to be exceeded. For instance, improperly made connections or improperly installed antennas can disturb the network and lead to malfunctions in the Wireless CPU® or equipment. 6.4.1.
It is recommended that the integrator use a cable with a maximum resistance of 5 milli ohm for the ground connection. AREF and GND are connected at a single point inside the Wireless CPU®. NOTE 6.4.2.3 They must not be joined together in the application. Audio Use coupling capacitors on MICIP / MICIN lines if the application does not use the Wireless CPU®’s bias voltage. See also 4.9.3 Microphone Signals (MICIP, MICIN). 6.4.2.4 Software Upgrade There is one way of updating the firmware in the GR64.
6.5.2 Antenna Type Users should ensure that they choose the right type of antenna for the Wireless CPU®. The antenna must be designed for the frequency bands deployed in the regions that the Wireless CPU® is being used. For fixed locations this may be dual bands (for example E-GSM900/GSM1800 in Europe; GSM850/GSM1900 in North America). For applications which are mobile, users should consider whether three or all four GSM bands could be encountered.
Minimize the use of extension cables, connectors and adapters. Each additional cable, connector or adapter will result in additional loss of signal power. 6.5.5 Possible Communication Disturbances Communication disturbances can adversely affect the quality of wireless links, including the following causes: • Noise can be caused by electronic devices and radio transmitters. • Path-loss occurs as the strength of the received signal steadily decreases in proportion to the distance from the transmitter.
7 Embedded Applications The Wireless CPU® has the capability to store and run customer written code in the form of a script during the processor’s idle time, through the use of an on board interpreter. 7.
7.2.1 Limitations Since the Wireless CPU® is processing the script using its own memory, limitations are placed onto the scripts that are run. A direct comparison cannot be made to a fully compiled C program in terms of size, but a gauge of script size is that if each line were 64 characters long (not counting comments or any form of white space) in the script then the script could be about 2000 lines long.
8 TCP/IP Stack An on board IP/TCP/UDP stack has been integrated into the software negating the need for the customer to implement one in their own code base. This is accessible by using an embedded application (see section 9) using intrinsic functions. 8.1 Implementation The following types of commands allow various functions: • Open/closing IP connections - Negotiates/closes an IP address with the web server. • Send/Receive TCP packets - Performs all TCP operations to send and receive packets.
9 Technical Data 9.1 Mechanical Specifications Refer to Figure 3 & Figure 4 for reference to mechanical features. Mechanical Feature Variant Value Length 50 mm Width 33 mm Thickness (see illustration below) Weight without SIM holder 3.3 mm with SIM holder 5.9 mm without SIM holder 8 grams with SIM holder 9 grams 3.3 Figure 31: Thickness of Wireless CPU® variant without SIM holder 5.
9.2 Power supply voltage, normal operation Parameter VCC Supply voltage Mode Limit Nominal 3.6 V Min 3.2 V Max 4.5 V Absolute maximum -0.3 to 6.5 V voltage range <100mV @ <200kHz Maximum supply ripple Maximum allowable voltage drop Maximum current consumed ! WARNING <20mV @ >200kHz Transmission burst 200mV 2250 mA (peak) Full power (2W) transmit 2100 mA (average) Stresses in excess of the absolute maximum limits can cause permanent damage to the device.
9.4 9.5 SIM card Parameter 1.8V 3.0V 5.
Test Case Test Summary Ref Standard Temp (low) : min storage Temp (high) : max storage Thermal Shock Test 6 min dwell at each extreme IEC 60068-2-14 0.
Test Case Test Summary Ref Standard Freq: 10-60 Hz, Freq : 60-500 constant displacement ≡±0.35mm Sinusoidal Vibration acceleration ≡ 5 g Hz, constant Sweep velocity: 1 oct/min IEC 60068-2-6 Sweeps: 5 per axis Axis: 3 axis (x, y, z) per device Power Spectral Density: 5 Hz 0.10 m2/s3 12 Hz 2.20 m2/s3 20 Hz 2.20 m2/s3 Random Vibration 200 Hz0.04 m2/s3 IEC 60068-2-34 500 Hz0.
10 Regulatory Notices The GR64 described in this manual conforms to the Radio and Telecommunications Terminal Equipment (R&TTE) directive 99/5/EC with requirements covering EMC directive 89/336/EEC and Low Voltage directive 73/23/EEC. The product fulfils the requirements according to 3GPP TS 51.010-1, EN 301 489-7 and EN60950. This device complies with Part 15 of the FCC rules.
GR64 Integrators’ Manual Page: 101/106 This document is the sole and exclusive property of WAVECOM. Not to be distributed or divulged without prior written agreement. Ce document est la propriété exclusive de WAVECOM.
GR64 Integrators’ Manual Page: 102/106 This document is the sole and exclusive property of WAVECOM. Not to be distributed or divulged without prior written agreement. Ce document est la propriété exclusive de WAVECOM.
GR64 Integrators’ Manual Page: 103/106 This document is the sole and exclusive property of WAVECOM. Not to be distributed or divulged without prior written agreement. Ce document est la propriété exclusive de WAVECOM.
DEVELOPERS KIT GR64 Integrators’ Manual Page: 104/106 This document is the sole and exclusive property of WAVECOM. Not to be distributed or divulged without prior written agreement. Ce document est la propriété exclusive de WAVECOM.
11 Introduction to the Universal Developer’s Kit The Wavecom universal developer’s kit (UDK) is designed to get the integrator started quickly. It contains all the hardware the integrator will need to begin the development of an application. The only items the integrator needs to provide are; a Wireless CPU®, a computer, a SIM card with a network subscription, and knowledge of programming with AT commands.
GR64 Integrators’ Manual Page: 106/106 This document is the sole and exclusive property of WAVECOM. Not to be distributed or divulged without prior written agreement. WAVECOM S.A. - 3 esplanade du de Foncet - 92442 Issy-les-Moulineaux Cedex -ou France - Tel:à +33(0)1 46sans 29 08 00 autorisation - Fax: +33(0)1 46 29 08 08 Ce document est la propriété exclusive WAVECOM. Il ne peut être communiqué divulgué des tiers son préalable Wavecom, Inc. - 430 Davis Dr.
