Specifications

The two SW power state control signals are not included in Figure 5. This figure only
shows the HW-signals.
Figure 6: Power Management State Diagram
Figure 6 shows the impact five of the six control signals, listed above, have on the
Power Management status of the Wireless CPU. The AT*E2RESET is described
individually in
3.2.6 below.
If a PSC-signal is held active (PON_H high, ON/OFF low, etc.) while the Wireless CPU is
active, it is not possible for another PSC-signal to generate a power down request.
Any such request will be denied. If a valid power down request is generated while a
CPS is available, the Wireless CPU will be set to “Charge Only”-mode.
3.2.1 ON/OFF
This system connector signal provides a power up feature similar to a normal cell
phone on/off button, i.e. a low pulse will toggle between On-state and Off-state.
This signal is weekly pulled up to VCC in the Power Management ASIC by a constant
current source.
Table 2: ON/OFF signal characteristics
Input Characteristics
Parameter Description
Min. Avg. Max.
Unit
I
IL
-60 -25 -12 μA
I
IH
Input current
0 1 μA
V
IL
Low level detection limit 0.2*VCC V
V
IH
High level detection limit 0.8*VCC V
t
Low
Required time for detection 450 ms
Gx64 APPLICATION NOTE
This document is the sole and exclusive property of WAVECOM. Not to be distributed or divulged without prior written agreement.
Ce document est la propriété exclusive de WAVECOM. Il ne peut être communiqué ou divulgué à des tiers sans son autorisation préalable
Power Management
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