Specifications

Product Technical Specification & Customer Design Guidelines
Interfaces
TOUTdelay
TSYNC-CLK
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WA_DEV_Q64_PTS_001-003 January 9, 2009
TCLK-cycle
TIN-hold
TIN-setup
PCM-SYNC
PCM-CLK
PCM-IN
PCM-OUT
SLOT 0 bit 15 SLOT 0 bit 14 SLOT 0 bit 13SLOT 5 bit 0
SLOT 0 bit 15 SLOT 0 bit 14 SLOT 0 bit 13SLOT 5 bit 0
Figure 42 : PCM Sampling waveform
3.19.2
Pin Description
Signal Pin I/O I/O type Reset state Description
number
51
PCM-SYNC O 2V8 Undefined Frame synchronization 8Khz
52
PCM-CLK O 2V8 Undefined Data clock
48
PCM-OUT O 2V8 Undefined Data output
47
PCM-IN I 2V8 Undefined Data input
See chapter
3.4, “Electrical Information for Digital I/O” on page 30 for 2V8-1, 2V8-2, pull-up and open drain
voltage characteristics and for Reset state definition.
.