Specifications

Product Technical Specification & Customer Design Guidelines
Interfaces
With the Open AT
®
Software Suite 1.0 / V2.0 when the UART1 service is run the
multiplexed signals are unavailable for other purposes. Likewise, if one or more
GPIOs (of this table) are allocated the UART1 service is unavailable.
The rising time and falling time of the reception signals (mainly DTM1) must be
shorter than 300 ns.
Recommendation:
The Q64 is designed to operate with all serial interface signals. It is mandatory to use
RTS1 and CTS1 for hardware flow control in order to avoid data corruption during
transmission.
5-wire serial interface hardware design:
• Signal: DTM1*, DFM1*, RTS1*, CTS1*
• The signal DTR1* must be managed following the V24 protocol signalling if we
want to use the slow idle mode
• Please refer to the document [4] AT Command Interface Guide for Open AT
®
Firmware v6.5
for more information.
4-wire serial interface hardware design:
• DTM1*, DFM1*, RTS1*, CTS1*
• The signal DTR1* must be configured at the low level.
• Please refer to the document [4] AT Command Interface Guide for Open AT
®
Firmware v6.5
for more information.
2-wire serial interface hardware design:
• It is possible for connected external chip but not recommended (and forbidden
for AT command or modem use)
• The flow control mechanism must be managed by the customer.
• DTM1*, DFM1*
• The signal DTR1* must be configured at the low level.
• The signals RTS1*, CTS1* are not used, please configure the AT command
(AT+IFC=0,0 see document
[4] AT Command Interface Guide for Open AT
®
Firmware v6.5
).
• The signal RTS1* must be configured at the low level.
• Please refer to the document [4] AT Command Interface Guide for Open AT
®
Firmware v6.5
for more information.
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WA_DEV_Q64_PTS_001-003 January 9, 2009