Specifications

Product Technical Specification & Customer Design Guidelines
Interfaces
AC characteristics
Signal Description Minimum Typ Maximum Unit
SCL-freq I²C clock frequency 100 400 KHz
T-start Hold time START condition 0.6 μs
T-stop Setup time STOP condition 0.6 μs
T-free Bus free time, STOP to START 1.3 μs
T-high High period for clock 0.6 μs
T-data-hold Data hold time 0 0.9 μs
T-data-setup Data setup time 100 ns
3.5.2 Pin Description
Signal Pin
number
I/O I/O type Reset state Description Multiplexed
with
SDA
29
I/O Pull-up Pull-up* Serial Data GPIO13
SCL
30
O Pull-up Pull-up* Serial
Clock
GPIO14
*SDA and SCL pull-up are about 10K Ω
See chapter
3.4, “Electrical Information for Digital I/O” on page 30 for 2V8-1, 2V8-2, pull-up and open drain
voltage characteristics and for Reset state definition.
The two lines are internally pulled up with each 1 KΩ resistor to voltage 2.8V (VREF)
inside the Q64 Wireless CPU
®
.
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This document is the sole and exclusive property of WAVECOM. Not to be distributed or divulged without
prior written agreement.
WA_DEV_Q64_PTS_001-003 January 9, 2009
Customer
application
Q64
SDA
SCL
2.8V
1K1K
Figure 4: I²C bus configuration inside the Wireless CPU
®
The I²C bus is compliant with the Standard mode (baud rate 100Kbit/s) and the Fast
mode (baud rate 400Kbit/s).