Specifications

Product Technical Specification & Customer Design Guidelines
Interfaces
© Confidential
Page: 32 / 116
This document is the sole and exclusive property of WAVECOM. Not to be distributed or divulged without
prior written agreement.
WA_DEV_Q64_PTS_001-003 January 9, 2009
Data valid
3.5 I2C Bus
3.5.1 Features
The I2C interface includes a clock signal (SCL) and a data signal (SDA) complying
with a 100Kbit/s-standard interface (standard mode: s-mode).
3.5.1.1 Characteristics
The I²C bus is always master.
The maximum speed transfer range is 400Kbit/s (Fast mode: f-mode).
For more information on the bus, see document
[7] “I²C Bus Specification”, Version
2.0, Philips Semiconductor 1998
.
3.5.1.2 I²C Waveforms
I²C bus waveform in master mode configuration:
SCL
SDA
Data valid
T-free
T-start
T-high
T-data-
setup
T-data-
hold
T-stop
SCL-freq
Figure 3: I²C Timing diagrams, Master