Specifications

7.4. SOFTWARE DESIGN
functions. As outlined in the hardware design section (Section 7.3.5), an
exchange consists of one byte transmitted to the slave followed by nine bytes
received.
The I
2
C communication process has 24 possible states and is blocking.
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Once initiated (by changing into the “send start” state), the FSM runs to
completion, be that because of a successful exchange or because of a time-out
due to an error. This is the only blocking FSM in the uplink module. The
reason why it is possible to create a blocking FSM for this component and
not any of the others is that the e ntire I
2
C exchange is expe cted to complete
within 250ms. The GSM module, for example, can require over 90 seconds
to complete an upload. If a process were to block the processor for close to
one second or more, it would most importantly preventing reliable peripheral
polling.
To initiate an I
2
C exchange, the address of the target slave device must
be stored in a global variable “I
2
C slave address” and the data byte which
is transmitted before receiving data must be placed into “I
2
C TX data”.
The starting state then sends the first start bit and sets a time-out period of
250ms. If communication does not complete before this time-out, then the
state changes to “timed out” and the FSM exists. If communication failed
because of an error (such as handshaking error) then the I
2
C state changes to
“communication error”. If communication was successful, the nine received
data bytes are placed into the global data array “I
2
C RX buffer” and the
I
2
C state changed to “communication ok”. These I
2
C state and the received
data array keep their states for the requesting application to take appropriate
action.
7.4.6 Timer FSM
The processor runs two timers in addition to the RTC outlined above. One
is used to create delays or measure times in the range of 0 - 255 milliseconds
and is based around the hardware Timer3 module (“timer ms”). The second
is used to create delays or measure times in the order of seconds and uses
5
A blocking process is one which prevents any other process from executing (in this
case any other FSMs from stepping) while it is running.
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