User guide

CM52 Integrators’ Manual
WI_DEV_CM52_UGD_001-001
Page 29 of 53
CM52 Integrators’ Manual
2.6.1.2 Timing
Timing shall be according to the following diagram (see
Figure 13: PCM Timing Diagram). The
signals in the diagram shall be interpreted according to the following relation.
Figure 13: PCM Timing Diagram
The meaning and value of the timing parameters are described in
Table 18.
Name Description Min Typical Max Unit
PCM_SYNC cycle time. 125 Us t
SYNC
PCM_SYNC frequency 8.0 kHz
t
SYNCA
PCM_SYNC asserted time. 62.4 62.5 Us
t
SYNCD
PCM_SYNC de-asserted time. 62.4 62.5 Us
t
SU(SYNC)
PCM_SYNC setup time to PCM_CLK
rising.
1.95 us
t
H(SYNC)
PCM_SYNC hold time after PCM_CLK
falling.
1.95 us
PCM_CLK cycle time. 7.8 us t
CLK
PCM_CLK frequency 128 kHz
t
CLKH
PCM_CLK high time. 3.8 3.9 us
t
CLKL
PCM_CLK low time. 3.8 3.9 us
t
PDLD
Propagation delay from PCM_CLK
rising to PCM_DLD valid.
50 ns
T
SU(ULD)
PCM_ULD setup time to PCM_CLK
falling.
70 ns
T
H(ULD)
PCM_ULD hold time after PCM_CLK
falling.
20 ns
Table 18: PCM Timing Parameters
This document is the sole and exclusive property of WAVECOM. Not to be distributed or divulged without prior written agreement.
Ce document est la propriété exclusive de WAVECOM. Il ne peut être communiqué ou divulgué à des tiers sans son autorisation préalable