Specifications

Wireless CPU
®
Q24 Series
Interfaces
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This document is the sole and exclusive property of WAVECOM. Not to be distributed or divulged without
prior written agreement.
WM_PRJ_Q24NG_PTS_001-004
January 16, 2007
If used (as an emergency reset), it must be driven either by an open collector or an
open drain output:
Figure 12: RST pin connection
For the implementation of the reset interface, refer to Customer Design Guidelines
[6].
3.17.2 Reset Sequence
To activate the "emergency "reset sequence, the ~RST signal must be set to low for
500 μs minimum.
As soon as the reset is completed, the AT interface answers "OK" to the application.
In this case, the application must send AT↵. If the application manages hardware
flow control, the AT command may be sent during the initialization phase.
Another solution is to use the AT+WIND command to obtain an unsolicited status
from the Wireless CPU
®
.
For further details, refer to the AT commands documentation
[4].
Figure 13: Reset sequence diagram
3.18 External Interrupt (~INTR)
The Wireless CPU
®
Q24 Series provide an external interrupt input ~INTR. This input is
highly sensitive.
An interrupt is activated on a falling edge.
If this signal is not used, it may be left open.
If used, this input must be driven either by an open collector or an open drain output.
GND
~RST
External reset
External reset
Status:
Ready
ON mode
Min 500µs
Typ: 2ms
Ready
Reset mode
SIM and network dependent