Specifications

Wireless CPU
®
Q24 Series
Interfaces
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This document is the sole and exclusive property of WAVECOM. Not to be distributed or divulged without
prior written agreement.
WM_PRJ_Q24NG_PTS_001-004
January 16, 2007
3.16 BOOT (optional)
This input may be used to download software to the Flash memory of the Wireless
CPU
®
.
For applications based on AT commands, this is a backup download procedure (refer
to document
[6] Customer Design Guidelines).
The internal BOOT procedure starts when this pin is low during Wireless CPU
®
reset.
Caution:
• This BOOT pin must be left open for normal use or X-modem download.
• The nominal firmware download procedure uses the X-modem.
In Internal BOOT mode, low level must be set through a 1KΩ resistor.
• BOOT = logical state 0, for download mode and
• BOOT = logical state 1, for normal mode.
Pin description
Signal Pin I/O I/O type Reset state Description
BOOT 12 I CMOS (C5) Pull-up to 2V8 Flash Downloading
(C5): To obtain more details on I/O type, refer to the section 4.2 "I/O Circuit diagram"
3.17 Reset Signal (~RST)
3.17.1 General Description
The reset signal is used to force a reset procedure by providing low level, for at least
500 μs.
The Wireless CPU
®
remains in reset mode as long as the ~RST signal is held low.
The reset process is activated either by the external ~RST signal or automatically by
an internal signal (coming from a reset generator).
• ∼RST = logical state 0, for Wireless CPU
®
Reset and
• ∼RST = logical state 1, for normal mode.
Note:
A software reset is always preferred to a hardware reset.
The automatic reset is activated during a power-ON sequence.
During a power-ON sequence, the ~RST pin of the Wireless CPU
®
is set to the logical
state 0.
Caution:
• During a power-ON sequence of the Wireless CPU
®
, avoid to apply any voltage
in the ~RST pin