Specifications

Wireless CPU
®
Q24 Series
Interfaces
©Confidential Page: 54 / 83
This document is the sole and exclusive property of WAVECOM. Not to be distributed or divulged without
prior written agreement.
WM_PRJ_Q24NG_PTS_001-004
January 16, 2007
3.15.2 Operating Sequences
3.15.2.1 Power-ON
Once the Wireless CPU
®
is supplied, the ON/~OFF signal must be asserted high
during a delay of T
on-hold
(Hold delay on the ON/~OFF signal) to power-ON.
After this delay, once the firmware has completed its power-up sequence, an internal
logic maintains the Wireless CPU
®
in power-ON condition.
You must not de-assert this ON/~OFF signal before this internal logic is internally
asserted by the firmware; the Wireless CPU
®
would not start-up otherwise.
Figure 10: Power-ON sequence diagram
The duration of the firmware power-up sequence depends on several factors:
• firmware version used by the Wireless CPU
®
• need to perform a recovery sequence if the power has been lost during a flash
memory modification
Other factors have a minor influence
• number of parameters stored in EEPROM by the AT commands received so far
• ageing of the hardware components, especially the flash memory
• temperature conditions
Internal RESET
42ms Typ
SIM, memory and
network dependent
Status:
OFF mode Reset mode
ON mode
Ready
AT command:
“AT” is send, “OK” is received
VDD
ON/~OFF
Ton
hold