Specifications

Wireless CPU
®
Q24 Series
Interfaces
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This document is the sole and exclusive property of WAVECOM. Not to be distributed or divulged without
prior written agreement.
WM_PRJ_Q24NG_PTS_001-004
January 16, 2007
Pin description
Signal Pin I/O I/O type Reset state Description
Multiplexed
with
CT103/TXD1 39 I CMOS
High
impedance
Transmit
serial data
CT104/RXD1 32 O
CMOS
1X (C3)
2V8
Receive serial
data
CT105/RTS1 30 I CMOS
High
impedance
Request To
Send
CT106/CTS1 37 O
CMOS
1X (C1)
2V8 Clear To Send
CT107/DSR1 36 O
CMOS
1X (C3)
2V8
Data Set
Ready
CT108-
2/DTR1
34 I CMOS
High
impedance
Data Terminal
Ready
CT109/DCD1 51 O
CMOS
2X (C1)
High
impedance
Data Carrier
Detect
GPIO3
CT125/RI1 54 O
CMOS
2X (C1)
High
impedance
Ring Indicator
GPIO2
CT102/GND
Shielding
legs
Ground
(C1) and (C3): To obtain more details on I/O type, refer to section 4.2 "I/O Circuit diagram"
Caution:
• The rise and fall time of the reception signals (mainly CT103) must be less
than 200 ns
• The Wireless CPU
®
Q24 Series are designed to operate using all the serial
interface signals. In particular, it is necessary to use RTS and CTS signals for
hardware flow control in order to avoid data corruption during transmission