Specifications

Wireless CPU
®
Q24 Series
Interfaces
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prior written agreement.
WM_PRJ_Q24NG_PTS_001-004
January 16, 2007
3.3 Electrical Information for Digital I/O
All digital I/O comply with a 3 volt CMOS.
Electrical characteristics
Parameter I/O type min Max Conditions
VIL CMOS -0.5 V 0.8 V
VIH CMOS 2.1 V 3.0 V
VOL 1X -0.2V 0.2 V IOL = -1 mA
- 2X -0.2V 0.2 V IOL = -2 mA
- 3X -0.2V 0.2 V IOL = -3 mA
VOH 1X 2.55 V 2.95V IOH = 1 mA
- 2X 2.55 V 2.95V IOH = 2 mA
- 3X 2.55 V 2.95V IOH = 3 mA
3.4 Serial Interface
3.4.1 SPI Bus
The SPI bus includes a CLK signal (SPI_CLK), an I/O signal (SPI_IO), and an EN signal
(SPI_EN) complying with the SPI bus standard.
The frequency clock is programmable from 812 kHz to 13 MHz.
Pin description
Signal Pin I/O I/O type Reset state Description Multiplexed
with
SPI_CLK 10 O CMOS 1X (C5)
Pull-up to 2V8
SPI Serial
Clock
SCL
SPI_IO 8 I/O CMOS / CMOS 1X
(C2)
Pull-up to 2V8
SPI Data SDA
SPI_EN 28 O CMOS 1X (C3) 2V8 SPI Enable GPO3
(C2), (C3) and (C5): To obtain more details on I/O type, refer to section 4.2 "I/O Circuit diagram"