Specifications

Wireless CPU
®
Q24 Series
Interfaces
©Confidential Page: 19 / 83
This document is the sole and exclusive property of WAVECOM. Not to be distributed or divulged without
prior written agreement.
WM_PRJ_Q24NG_PTS_001-004
January 16, 2007
3 Interfaces
Note:
Some of the Wireless CPU
®
Q24 Series interface signals are multiplexed in order to
limit the total number of pins. But this architecture imposes some restrictions.
Example:
If the SPI bus and 2-wire bus are multiplexed and if the SPI bus is used, then the 2-
wire bus is not available.
Caution:
To power-ON the Wireless CPU
®
Q24 Series correctly and to avoid any damage, all
external signals must be inactive when the Wireless CPU
®
Q24 Series is OFF.
3.1 General Purpose Connector (GPC)
A 60-pin connector, with 0.5 mm pitch, is provided to interface the Wireless CPU
®
Q24 Series with a customer application board containing either an LCD module, or a
keyboard, a SIM connector, a battery connection, etc.
The GPC is made by the KYOCERA / AVX group with the following reference:
• 14 5087 060 930 861.
The matting connector has the following reference:
• 24 5087 060 X00 861.
For further details, refer to section
6.1 General Purpose Connector Data Sheet.