Specifications

Wireless CPU
®
Q24 Series
Interfaces
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WM_PGM_Q24NG_PTS_001-005 November 20, 2007
If used (as an emergency reset), it must be driven either by an open collector or an
Figure 12: RST pin connection
For the implementation of the reset i rfa to Cus uidelines [6].
3.17.2 Reset Sequence
To activate the "emergency "rese signal must be set to low for
500 µs minimum.
As soon as t e a rs th lication.
In this case, the application must send AT↵. If the application manages hardware
flow control, the AT command may be se
Another solu e AT+WIND command t obta ed status
from the W
For further details, refer to the AT commands documentation [4].
Figure 13: Reset sequence diagram
.18 External Interrupt (~INTR)
he Wireless CPU
®
Q24 Series provide an external interrupt input ~INTR. This input is
ive.
iven either by an open collector or an open drain output.
open drain output:
~RST
GND
External reset
nte ce, refer tomer Design G
t sequence, the ~RST
he reset is completed, the AT interfac nswe "OK" to e app
nt during the initialization phase.
tion is to use th
ireless CPU
®
.
o in an unsolicit
3
T
highly sensit
An interrupt is activated on a falling edge.
If this signal is not used, it may be left open.
If used, this input must be dr
External reset
Status:
Ready
ON mode
Min 500µs
Typ: 2ms
Ready
Reset mode
SIM and network dependent