Specifications

Wireless CPU
®
Q24 Series
Interfaces
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prior written agreement.
WM_PGM_Q24NG_PTS_001-005 November 20, 2007
software to the Flash memory of the Wireless
PU
®
.
or applications based on AT commands, this is a backup download procedure (refer
document [6] Customer Design Guidelines).
The internal BOOT procedure starts when
®
reset.
3.16 BOOT (optional)
This input may be used to download
C
F
to
this pin is low during Wireless CPU
Caution:
• This BOOT pin must be left open for normal use or X-modem download.
ownload procedure uses the X-modem.
gical state 0, for download mode and
• The nominal firmware d
In Internal BOOT mode, low level must be set through a 1KΩ resistor.
• BOOT = lo
• BOOT = logical state 1, for normal mode.
Pin description
Signal Pin I/O I/O type Reset state Description
BOOT 12 I CMOS (C5) Pull-up to 2V8 Flash Downloading
(C5): To obtain more details on I/O type, refer to the section 4.2 "I/O Circuit diagram"
.17 Reset Signal (~RST)
.1 General Description
force a reset procedure by providing low level, for at least
00 µs.
The Wireless CPU
®
remains in reset mode as long as the ~RST signal is held low.
The reset process is acti nal or automatically by
an internal signal (coming from a reset generator).
∼RST = logical state 0, for Wireless CPU
®
Reset and
3
3.17
The reset signal is used to
5
vated either by the external ~RST sig
•
• ∼RST = logical state 1, for normal mode.
Note:
A software reset is always preferred to a hardware reset.
er-ON sequence.
state 0.
The automatic reset is activated during a pow
During a power-ON sequence, the ~RST pin of the Wireless CPU
®
is set to the logical
Caution:
• During a power-ON sequence of the Wireless CPU
®
, avoid to apply any voltage
in the ~RST pin