Specifications

Wireless CPU
®
Q24 Series
Interfaces
©Confidential Page: 54 / 83
This document is the sole and exclusive property of WAVECOM. Not to be distributed or divulged without
prior written agreement.
WM_PGM_Q24NG_PTS_001-005 November 20, 2007
3.1
3.15.2.
Once th
during a
Aft
logic ma
internally
ass d
Figure 10: Power-ON sequence diagram
sequence depends on several factors:
• firmware version used by the Wireless CPU
®
• need to perform n lost during a flash
memory modification
Othe ve a minor influence
ts, especially the flash memory
temperature conditions
5.2 Operating Sequences
1 Power-ON
e Wireless CPU
®
is supplied, the ON/~OFF signal must be asserted high
delay of T
on-hold
(Hold delay on the ON/~OFF signal) to power-ON.
er this delay, once the firmware has completed its power-up sequence, an internal
intains the Wireless CPU
®
in power-ON condition.
You must not de-assert this ON/~OFF signal before this internal logic is
erte by the firmware; the Wireless CPU
®
would not start-up otherwise.
The duration of the firmware power-up
a recovery sequence if the power has bee
r factors ha
• number of parameters stored in EEPROM by the AT commands received so far
• ageing of the hardware componen
•
Internal RESET
42ms Typ
SIM, memory and
network dependent
Status:
OFF mode Reset mode
ON mode
Ready
AT command:
“AT” is send,
“ OK” is received
VDD
Ton
hold
ON/~OFF