Specifications

Wireless CPU
®
Q24 Series
Interfaces
©Confidential Page: 37 / 83
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prior written agreement.
WM_PGM_Q24NG_PTS_001-005 November 20, 2007
3.9 General Purpose Input/Output
The Wireless CPU
®
Q24 Series provide:
• 4 General Purpose Output,
se Input.
They are used to control any external devices such as an LCD or a Keyboard
bac
Note
• 3 General Purpose I/O,
• 1 General Purpo
klight.
:
would allow users to set a high logic
Pin description
GPIO0 has a 100K pull-down resistor, which
state to the pin during reset state.
Signal Pin I/O I/O type Reset state Description
Multiplexed
with
G 4 I/O
CMOS / CMOS 2X
(C1)
100K
down to 0V
eral Purpose
I/O
CT106/CTS2
PIO0 2
pull- Gen
GPIO1 52 I/O
(C1) imp
FLASH LED
CMOS / CMOS 2X High General Purpose
edance O
GPIO4 53 I/O
/ CMOS 2X al Purpose CMOS
(C1) impedance
High Gener
I/O
GP
(C1) impedance
n
I/O
CT105/RTS2
IO5 35 I/O
CMOS / CMOS 2X High Ge eral Purpose
G 6
UX
PO0 2 O CMOS 3X (C3) 2V8
General Purpose
O
SPI_A
GPO1 22 O CMOS 3X (C3) 0V
General Purpose
O
GPO2 20 O CMOS 3X (C3)
General Purpose
O
CT104/RXD2
2V8
G OS
en
O
PO3 28 O CM 3X (C3)
2V8
G eral Purpose
SPI_EN
GPI 18 I CMOS (C4)
CT103/TXD2
Pull-down to Gen
0V I
eral Purpose
(C1), (C3) and (C4): To obtain more details on I/O type, refer to section 4.2 "I/O Circuit diagram"
The following GPIOs are not available (reserved) with a Wireless CPU
®
running with an AT commands firmware:
A
A
A
T
T
T