Specifications

Wireless CPU
®
Q24 Series
Interfaces
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prior written agreement.
WM_PGM_Q24NG_PTS_001-005 November 20, 2007
3. iliar ria nk 2
For specific applications, an auxiliary serial interface (UART2) is available on the
Wireless CPU
®
Q Serie
E.g. Bluetooth connectivity: See AT commands interface guide (Bluetooth) [5].
7 Aux y Se l Li (UART )
24 s.
Figure 5: UART2 Serial Link signals
Pin description
Signal Pin I/O I/O type Reset state Description
Multiplexed
with
CT1
I CMOS (
wn to mit
03 /
18
TXD2
C4)
Pull do
0V
Trans serial
data
GPI
CT104 /
RXD2
20 O
CMOS 1
(C3)
Receive serial
data
X
2V8
GPO2
CT106 /
CTS2
24 O
CM
(C1) pedance
en GPIO0
OS 2X High
im
Clear To S d
CT105 /
RTS2
35 I CMOS
pedance
o end GPIO5
High
im
Request T S
(C1), (C3) and (C4): To obta , refer to ection 4.2 " O Circuit am"
ace
cription
llowing five signals
IM po
et.
SIM_CLK: Clock.
/O port.
• SIM_PRES: SIM Card detection.
The SIM hrough an external SIM
dr
conc
in more details on I/O type s I/ diagr
3.8 SIM Interf
3.8.1 General Des
The fo are available:
• SIM_VCC: S wer supply.
• SIM_RST: Res
•
• SIM_DATA: I
interface controls a 3V / 1V8 SIM (and a 5V SIM t
iver). This interface is fully compliant with the GSM 11.12 recommendations
erning SIM functions.