Specifications

Wireless CPU
®
Q24 Series
Interfaces
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WM_PGM_Q24NG_PTS_001-005 November 20, 2007
Pin description
Signal Pin I/O I/O type Reset state Description
Multiplexed
with
CT103/TXD1 39 I CMOS
impedance serial data
High Transmit
CT104/RXD1 32 O
CMOS
1X (C3)
2V8
Receive serial
data
CT105/RTS1 30 I CMOS
High
impedance
Request To
Send
CT106/CTS1 37 O
CMOS
1X (C1)
2V8 Clear To Send
CT107/DSR1 36 O
CMOS
1X (C3)
2V8
Data Set
Ready
CT108-
2/DTR1
34
impedance
erminal
Ready
I CMOS
High Data T
CT109/DCD1 51 O
CMOS
2X
High
e
Data Carrier
Detect
GPIO3
(C1) impedanc
CT125/RI1 54 O
CMOS
X (C
High
nce
Ring Indicator
GPIO2
2 1) impeda
CT102/GND
Shielding
g le s
Ground
(C1) and (C3): To obta s on I/O type, refer to s it diagram" in more detail ection 4.2 "I/O Circu
Caution:
e rise and me of th signals (mainly CT103) must be less
n n
e Wireless CPU
®
Q24 Series are designed to operate using all the serial
ls for
hardware flow control in order to avoid data corruption during transmission
• Th fall ti e reception
tha
• Th
200 s
interface signals. In particular, it is necessary to use RTS and CTS signa