Specifications

Wireless CPU
®
Q24 Series
Interfaces
©Confidential Page: 31 / 83
This document is the sole and exclusive property of WAVECOM. Not to be distributed or divulged without
prior written agreement.
WM_PGM_Q24NG_PTS_001-005 November 20, 2007
Pin description
Signal
Pin
number
I/O I/O type Reset state Description
ROW0 13 I/O CMOS / CMOS 1X Pull-down to 0V Row scan
ROW1 15 I/O CMOS / CMOS 1X Pull-down to 0V Row scan
ROW2 17 to 0V Row scan I/O CMOS / CMOS 1X Pull-down
ROW3 19 I/O CM Pull-down to 0V Row scan OS / CMOS 1X
ROW4 21 I/O CMOS / CMOS 1X Pull-down to 0V Row scan
COL0 23 I/O M ll Column scan CMOS / C OS 1X Pu -up to 2V8
COL1 25 I/O C X Pu 8 Column scan CMOS / MOS 1 ll-up to 2V
COL2 27 I/O Column scan CMOS / CMOS 1X Pull-up to 2V8
COL3 29 I/O C 1X Pull-up to 2V8 Column scan CMOS / MOS
COL4 31 I/O C u Column scan CMOS / MOS 1X P ll-up to 2V8
3 ria k (
A flexible 6-wire serial inter e lab mplying protocol signaling,
but e in .
The signals are:
• TX data (CT103/TX)
(CT104/RX)
t To d (C
• Clear To Send (CT106/CTS)
The two additional signals are:
• Ring Indicator (CT125/RI).
.6 Main Se l Lin UART1)
fac
e
is avai
rface) du
le, co
to a 2.8 volt
with V24
terface not with V28 (electrical int
• RX data
• Reques Sen T105/RTS)
• Data Terminal Ready (CT108-2/DTR)
• Data Set Ready (CT107/DSR)
• Data Carrier Detect (CT109/DCD).
Figure 4: UART1 Serial Link signals