Specifications

Wireless CPU
®
Q24 Series
Interfaces
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prior written agreement.
WM_PGM_Q24NG_PTS_001-005 November 20, 2007
3.4.2 SPI Auxiliary Bus
A second SPI Chip Enable (called SPI_AUX) must be used to add a second SPI
peripheral to the Wireless CPU
®
Q24 Series.
Pin description
Signal Pin I/O I/O type Reset state Description Multiplexed
with
SPI_CLK 10 O CMOS 1X (C5)
Pull-up to
2V8
SPI Serial
Clock
SCL
SPI_IO 8 I/O CMOS / CMOS 1X (C2)
Pull-up to
2V8
SPI Data SDA
SPI_AUX 26 O CMOS 1X (C3) 2V8
SPI Aux.
Enable
GPO0
(C2), (C3) and (C5): To obtain more details on I/O type, refer to section 4.2 "I/O Circuit diagram"
3.4.3 Two-wire Bus Interface (I
2
C)
The two-wire bus interface includes a CLK signal (SCL) and a DATA signal (SDA)
complying with a standard two-wire bus interface.
The frequency clock is programmable either to a 96 kHz or a 400 kHz.
Pin description
Signal Pin I/O I/O type Reset state Description
SCL 10 O CMOS 1X (C5) Pull-up to 2V8 Serial Clock
SDA 8 I/O CMOS / CMOS1X
(C2)
Pull-up to 2V8
Serial Data
(C2) and (C5): To obtain more details on I/O type, refer to section 4.2 "I/O Circuit diagram"