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Wireless CPU

Q24 Series

Product Technical Specification

Revision: 005

Date: November 2007

Summary of content (85 pages)

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WM_ Wireless CPU® Q24 Series Product Technical Specification Revision: 005 Date: November 2007
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Wireless CPU® Q24 Series Product Technical Specification Reference: WM_PGM_Q24NG_PTS_001 Revision: 005 Date: November 20, 2007 Powered by the Open AT® Software Suite confidential © Page: 1 / 83 This document is the sole and exclusive property of WAVECOM. Not to be distributed or divulged without prior written agreement.
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Wireless CPU® Q24 Series Document History Revision Date List of revisions 001 May 2006 Creation (Preliminary version) 002 September 2006 First update 003 November 2006 Update 004 January 16, 2007 Modification of the ON/ ~OFF paragraph Modification of the Battery charging paragraph Modification of electrical characteristics BAT-TEMP Integration of ATEX conformance information 005 November 7, 2007 confidential © Update Page: 2 / 83 This document is the sole and exclusive property of WAVEC
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Wireless CPU® Q24 Series Trademarks , , ®, “YOU MAKE IT, WE MAKE IT WIRELESS®”, WAVECOM®, Wireless Microprocessor®, Wireless CPU®, Open AT® and certain other trademarks and logos appearing on this document, are filed or registered trademarks of Wavecom S.A. in France and/or in other countries. All other company and/or product names mentioned may be filed or registered trademarks of their respective owners. Copyright This manual is copyrighted by WAVECOM with all rights reserved.
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Wireless CPU® Q24 Series Web Site Support General information about Wavecom and its www.wavecom.com range of products: www.wavecom.com/Q24Classic www.wavecom.com/Q24Plus www.wavecom.c www.wavecom.com/Q24Auto Carrier/Operator approvals: ® www.wavecom.com/approvals Open AT Introduction: www.wavecom.com/OpenAT Developer support for software and hardware: www.wavecom.com/forum confidential © Page: 4 / 83 This document is the sole and exclusive property of WAVECOM.
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Wireless CPU® Q24 Series Overview This Product Specification document defines and specifies the Wireless CPU® Q24 Series is available in four different GSM/GPRS Class 10 quad-band versions: • Q24 Classic: EGSM 900/1800/850/1900 MHz version with 32 Mb of Flash memory and 16 Mb of PSRAM (32/16), T° range [-20°C / +55°C]. • Q24 Plus: EGSM/GPRS 900/1800/850/1900 MHz version with 32 Mb of Flash memory and 16 Mb of PSRAM (32/16), T° range [-20°C / +55°C].
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Wireless CPU® Q24 Series Contents 1 References.......................................................................................................10 1.1 Reference Documents ..................................................................................... 10 1.1.1 Open AT® Software Documentation ........................................................ 10 1.1.2 AT Software Documentation................................................................... 10 1.1.3 Hardware Documents ...................
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Wireless CPU® Q24 Series 3.8.1 General Description................................................................................. 33 3.8.2 SIM Card Holder ..................................................................................... 35 3.9 General Purpose Input/Output ........................................................................ 37 3.10 Activity Status Indication ................................................................................ 38 3.11 Analog to Digital Converter (ADC) ..
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Wireless CPU® Q24 Series 6.2 6.3 6.4 6.5 6.6 6.7 7 SIM Card Reader............................................................................................. 75 Microphone .................................................................................................... 75 Speaker........................................................................................................... 75 Antenna Cable ................................................................................................
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Wireless CPU® Q24 Series Table of Figures Figure 1: Functional architecture .............................................................................. 17 Figure 2: Power supply during burst emission.......................................................... 21 Figure 3: Maximum voltage ripple (Uripp) versus Frequencies in GSM & DCS.......... 23 Figure 4: UART1 Serial Link signals .......................................................................... 31 Figure 5: UART2 Serial Link signals ...........
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Wireless CPU® Q24 Series References 1 References 1.1 Reference Documents For more details, several reference documents may be consulted. The Wavecom reference documents are provided in the Wavecom documents package contrary to the general reference documents, which are not Wavecom owned. Note: All below documents are related to V3.12 Open AT® Software and 6.57 Open AT® Firmware. Wavecom recommends that the developer should check the web site for the latest documentation 1.1.
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Wireless CPU® Q24 Series References 1.
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Wireless CPU® Q24 Series References Abbreviation Description GSM Global System for Mobile communications IF Intermediate Frequency INTR INTeRrupt I/O Input / Output LCD Liquid Crystal Display LED Light Emitting Diode LNA Low Noise Amplifier LSB Less Significant Bit MAX MAXimum MIC MICrophone MIN MINimum MMS Multimedia Message Service MS Mobile Station NOM NOMinal NTC Negative Temperature Coefficient PA Power Amplifier PBB PolyBrominated Biphenyl PBDE PolyBrominated Diphenyl
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Wireless CPU® Q24 Series References Abbreviation Description SPK SPeaKer SRAM Static RAM TDMA Time Division Multiple Access TU Typical Urban fading profile TUHigh Typical Urban, High speed fading profile TDMA Time Division Multiple Access TX Transmit TYP TYPical UART Universal Asynchronous Receiver-Transmitter VLSI Very Large Scale Integration VSWR Voltage Standing Wave Ratio ©Confidential Page: 13 / 83 This document is the sole and exclusive property of WAVECOM.
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Wireless CPU® Q24 Series General Description 2 General Description 2.1 General Information The Q24 Series are self-contained EGSM/GPRS 900/1800 and 850/1900 quad-band Wireless CPU®s with the following characteristics: Note: The Q24 classic is limited to GSM only (GPRS not supported). 2.1.1 Overall Dimensions Completely shielded: • Length: 58.4 mm • Width: 32.2 mm • Thickness: 3.
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Wireless CPU® Q24 Series General Description The Wireless CPU® Q24 Series are designed to integrate various types of specific process applications such as vertical applications (telemetry, multimedia, automotive). The Open AT® firmware offers a set of AT commands to control the Wireless CPU®. With this standard Operating System, some interfaces of the Wireless CPU® are not available since they are dependent on the peripheral devices connected to the Wireless CPU®.
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Wireless CPU® Q24 Series General Description 2.1.5 External RF Connection Interfaces The Wireless CPU® Q24 Series are available with different external RF connection configurations: Product reference UFL UFL or MMS Antenna pad IMP Position Bottom side Top side Top side Bottom side Q24 Classic X X X Q24 Plus X X X Q24 Extended X X X X X Q24 Automotive X 2.1.
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Wireless CPU® Q24 Series General Description 2.
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Wireless CPU® Q24 Series General Description 2.2.1 RF Functionalities The Radio Frequency (RF) range complies with the Phase II EGSM 900/DCS 1800 and GSM 850/PCS 1900 recommendations. The frequencies are given below: GSM band Transmit band (Tx) Receive band (Rx) GSM 850 EGSM 900 DCS 1800 PCS 1900 824 880 1710 1850 869 925 1805 1930 to to to to 849 MHz 915 MHz 1785 MHz 1910 MHz to to to to 894 MHz 960 MHz 1880 MHz 1990 MHz The Radio Frequency (RF) part is based on a specific quad-band chip.
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Wireless CPU® Q24 Series Interfaces 3 Interfaces Note: Some of the Wireless CPU® Q24 Series interface signals are multiplexed in order to limit the total number of pins. But this architecture imposes some restrictions. Example: If the SPI bus and 2-wire bus are multiplexed and if the SPI bus is used, then the 2wire bus is not available. Caution: To power-ON the Wireless CPU® Q24 Series correctly and to avoid any damage, all external signals must be inactive when the Wireless CPU® Q24 Series is OFF. 3.
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Wireless CPU® Q24 Series Interfaces The available interfaces on the GPC are shown below: OS 6.57 Section Name 3.4 3.5 3.6 3.7 3.8 3.9 Serial interface Keyboard Interface Main Serial Link Auxiliary Serial Link SIM interface General Purpose IO Activity status indication Analog to digital converter Audio Interface Battery charging interface ON/~OFF Boot Reset External interrupt VCC output Real Time Clock RF interface 3.10 3.11 0 3.14 3.15 3.16 3.17 3.18 3.19 3.20 3.
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Wireless CPU® Q24 Series Interfaces VBATTT Uripp Uripp t = 577 µs T = 4,615 ms Figure 2: Power supply during burst emission Two different inputs are provided for the power supply: • VBATT is used to supply the RF part and • VDD is used to supply the baseband part. VBATT: Directly supplies the RF components with 3.6 V. It is essential to keep a minimum voltage ripple at this connection in order to avoid any phase error. In particular, VBATT supplies the RF Power Amplifier.
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Wireless CPU® Q24 Series Interfaces Electrical characteristics Signal MIN NOM MAX VBATT 3.2 V 3.6 V 4.5 V * VDD 3.1 V 4.5 V *Max operating Voltage Standing Wave Ratio (VSWR) 2:1. 3.2.2 Power Supply Recommendation The VBATT voltage limits must be considered at any time. The worst condition is during the burst period transmission, when current consumption is at its highest. During this period, the VBATT voltage is minimum: • The output voltage of the power supply drops.
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Wireless CPU® Q24 Series Interfaces Maximal voltage ripple (Uripp) versus Frequency Freq. Uripp Max Freq. Uripp Max Freq.
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Wireless CPU® Q24 Series Interfaces 3.2.3 Power Consumption The Wireless CPU® Q24 Series support different power consumption modes: Working modes Comments OFF mode ALARM mode The Wireless CPU is in OFF mode. The Wireless CPU® is in OFF mode with RTC block running, when an ALARM occurs, the Wireless CPU® wakes-up automatically. The Wireless CPU® is synchronized with an RF GSM/GPRS network. The internal 26 MHz of the Wireless CPU® is constantly active.
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Wireless CPU® Q24 Series Interfaces 3.2.3.1 Power Consumption without Open AT® Processing The following measurement results are relevant only when: • There is no Open AT® application, • The Open AT® application is disabled, • No processing is required by the Open AT® application. INOM IMAX IMAX Unit average average peak Operating mode Parameters OFF Mode VBATT= 3.6V 16.5 18 µA Alarm Mode VBATT= 3.6V 18.5 20 µA Paging 9 10.5 11 150Rx mA Paging 2 13 13.5 150Rx mA Paging 9 2.
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Wireless CPU® Q24 Series Interfaces Cards and the results in brackets shown in the above table are the minimum and maximum currents measured from among all the SIM Cards used. 3.2.3.2 Power Consumption with Open AT® Software The power consumption with Open AT® software used is the Dhrystone application and the following consumption results were measured while performing on the Dhrystone application. INOM IMAX IMAX Unit average average peak Operating mode Parameters OFF Mode VBATT = 3.6V 16.
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Wireless CPU® Q24 Series Interfaces • Connected mode with one TX and one RX burst at PCL5 (33dBm) • GPRS class 10 transfer mode with two TX bursts and three RX burst at Gamma 3 (33dBm) • Slow Idle mode with a paging 9 (every 2 seconds) • Fast Idle mode with a paging 9 (every 2 seconds) The following waveform shows only the current form versus time: Current Waveform Connected mode with One TX burst at PCL5 and one RX burst Slow idle mode paging 9 GPRS Class 10 Transfer mode with two TX bursts at PC
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Wireless CPU® Q24 Series Interfaces 3.3 Electrical Information for Digital I/O All digital I/O comply with a 3 volt CMOS. Electrical characteristics Parameter I/O type min Max Conditions VIL CMOS -0.5 V 0.8 V VIH CMOS 2.1 V 3.0 V VOL 1X -0.2V 0.2 V IOL = -1 mA - 2X -0.2V 0.2 V IOL = -2 mA - 3X -0.2V 0.2 V IOL = -3 mA VOH 1X 2.55 V 2.95V IOH = 1 mA - 2X 2.55 V 2.95V IOH = 2 mA - 3X 2.55 V 2.95V IOH = 3 mA 3.4 Serial Interface 3.4.
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Wireless CPU® Q24 Series Interfaces 3.4.2 SPI Auxiliary Bus A second SPI Chip Enable (called SPI_AUX) must be used to add a second SPI peripheral to the Wireless CPU® Q24 Series. Pin description Signal Pin I/O SPI_CLK 10 SPI_IO 8 O I/O type Reset state Description CMOS 1X (C5) Pull-up to 2V8 SPI Serial Clock SCL Pull-up to 2V8 SPI Data SDA 2V8 SPI Aux.
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Wireless CPU® Q24 Series Interfaces 3.5 Keyboard Interface Equivalent circuit COLUMN 4 ROW 4 Key Release Detector ROW 0 Key Press 2V8 Select D Q Key COLUMN [0] 2V8 GND Row0 ROW [0] Detector COLUMN 0 Col0 Q D ROWCK GND Select CLOCK An AT command or Open AT® API allows the input key code to be obtained (see the AT+CMER command description). This code must then be processed by the application.
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Wireless CPU® Q24 Series Interfaces Pin description Signal Pin number I/O I/O type Reset state Description ROW0 13 I/O CMOS / CMOS 1X Pull-down to 0V Row scan ROW1 15 I/O CMOS / CMOS 1X Pull-down to 0V Row scan ROW2 17 I/O CMOS / CMOS 1X Pull-down to 0V Row scan ROW3 19 I/O CMOS / CMOS 1X Pull-down to 0V Row scan ROW4 21 I/O CMOS / CMOS 1X Pull-down to 0V Row scan COL0 23 I/O CMOS / CMOS 1X Pull-up to 2V8 Column scan COL1 25 I/O CMOS / CMOS 1X Pull-up to 2V8 Co
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Wireless CPU® Q24 Series Interfaces Pin description I/O type Pin I/O CT103/TXD1 39 I CMOS High impedance CT104/RXD1 32 O CMOS 1X (C3) 2V8 CT105/RTS1 30 I CMOS High impedance Transmit serial data Receive serial data Request To Send CT106/CTS1 37 O 2V8 Clear To Send CT107/DSR1 36 O CT1082/DTR1 34 I CT109/DCD1 51 O CT125/RI1 54 O CT102/GND Shielding legs CMOS 1X (C1) CMOS 1X (C3) CMOS CMOS 2X (C1) CMOS 2X (C1) Reset state Multiplexed with Signal 2V8 High impedance High
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Wireless CPU® Q24 Series Interfaces 3.7 Auxiliary Serial Link (UART2) For specific applications, an auxiliary serial interface (UART2) is available on the Wireless CPU® Q24 Series. E.g. Bluetooth connectivity: See AT commands interface guide (Bluetooth) [5].
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Wireless CPU® Q24 Series Interfaces Pin description Signal Pin I/O I/O type Reset state Description SIM_CLK 3 O 2V9/1V8 0V SIM Clock SIM_RST 5 O 2V9/1V8 0V SIM Reset SIM_DATA 7 I/O 2V9/1V8 0V SIM Data SIM_VCC 9 O 2V9/1V8 0V SIM Power Supply SIM_PRES 50 I 2V8 High impedance SIM Card Detect Caution: Disturbances (digital noise, ESD) in the SIM signals may interrupt the Wireless CPU® functionality, a good layout of these signals are recommended: • Ground separation between
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Wireless CPU® Q24 Series Interfaces high to low transition means that the SIM Card is removed. 3.8.2 SIM Card Holder An optional SIM Card holder may be placed on top of Wireless CPU®. This SIM Card holder does not use the SIM_PRES signal. Caution: Customers are advised to verify that the SIM Card environmental specification used is compliant with the Wireless CPU® Q24NG environmental specifications [3] (see the Wireless CPU® Q24NG Product Technical Specification WM_PRJ_Q24NG_PTS_001).
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Wireless CPU® Q24 Series Interfaces 3.9 General Purpose Input/Output The Wireless CPU® Q24 Series provide: • 3 General Purpose I/O, • 4 General Purpose Output, • 1 General Purpose Input. They are used to control any external devices such as an LCD or a Keyboard backlight. Note: GPIO0 has a 100K pull-down resistor, which would allow users to set a high logic state to the pin during reset state.
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Wireless CPU® Q24 Series Interfaces Pin description Signal Pin I/O I/O type Reset state Description Multiplexed with GPIO2 54 I/O CMOS / 2X (C1) High impedance General Purpose I/O CT125/RI1 GPIO3 51 I/O CMOS / 2X (C1) High impedance General Purpose I/O CT109/DCD1 (C1): To obtain more details on I/O type, refer to section 4.2 "I/O Circuit diagram" 3.10 Activity Status Indication The activity status indication signal may be used to drive a FLASH LED through an open collector transistor.
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Wireless CPU® Q24 Series Interfaces 3.11 Analog to Digital Converter (ADC) Equivalent circuit Q24 Series AUXV0 An Analog to Digital Converter is provided by the Wireless CPU® Q24 Series. This converter is a10-bit resolution, ranging from 0.9 to 2.775 V. Note: • The Q24NG ADC accuracy cannot be guaranteed for an ADC input level less than 0.9 V or greater than 2.775 V. • Q24NG ADC accuracy is guaranteed to +/- 10 mV for Q24NG input level between 0.9 V and 2.
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Wireless CPU® Q24 Series Interfaces 3.12 Audio Interface Two different microphone inputs and two different speaker outputs are supported. The Wireless CPU® Q24 Series also include an echo cancellation feature, which allows hands-free operation. Caution: When speakers and microphones are exposed to the external environment, it is recommended to add ESD protection on the audio interface lines. 3.12.
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Wireless CPU® Q24 Series Interfaces Microphone gain versus Max input voltage Using Controller 1 Transmit Gain (dB) Using Controller 2 Max Vin (mVrms) Transmit Gain (dB) Max Vin (mVrms) +30 43.80 -6.5 3031 +33 31.01 -6 2861 +36 21.95 0 1434 +39 15.54 +9.5 480 +42 11 +10 454 +45 7.79 +30.3 43.80 +48 5.51 +30.8 41.36 +51 3.9 +50.8 4.14 - - +51.3 3.90 * For more details, refer to the AT commands documentation [4] 3.12.1.
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Wireless CPU® Q24 Series Interfaces Pin description Signal Pin I/O I/O type MIC1P 42 I Analog MIC1N 44 I Analog Description Microphone 1 positive input Microphone 1 negative input Electrical characteristics MIC1 Electrical characteristics Parameters DC characteristics AC characteristics 100 Hz
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Wireless CPU® Q24 Series Interfaces Electrical characteristics MIC2 Electrical characteristics Parameters Internal biasing DC characteristics AC characteristics 100 Hz
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Wireless CPU® Q24 Series Interfaces The gain in the speaker outputs are internally adjusted and may be tuned by using AT commands (refer to the AT commands documentation [4]). Speaker gain versus Max output voltage Receive Gain (dB)* Max output level (Vrms) Max.speaker load (Ω) +2 1.74 150 0 1.38 50 -2 1.099 32 -4 0.873 32 -6 0.693 32 -8 0.551 32 -10 0.437 32 -12 0.347 32 -14 0.276 32 -16 0.219 32 -18 0.174 32 -20 0.138 32 -22 0.110 32 -24 0.087 32 -26 0.
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Wireless CPU® Q24 Series Interfaces 3.13 Buzzer Output 3.13.1 Hardware Description The buzzer interface is accessible through an open drain embedded on the Wireless CPU® Q24 Series. A buzzer may be directly connected between this output and VBATT. Equivalent circuit Q24 Series Pin description Signal Pin I/O I/O type Description BUZZER 49 O Analog Buzzer output Operating conditions Parameter Condition VOL IPEAK Min Max Unit Iol = 100mA 0.
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Wireless CPU® Q24 Series Interfaces 3.14 Battery Charging Interface 3.14.1 Hardware Description Caution: The battery charging interface does not allow the Wireless CPU® to be supplied and is only used to charge a battery connected to VBATT. Battery charging is performed through a switching transistor connecting the VBATT signal to the Charger (CHG_IN signal). The switching transistor is controlled by the operating system with two kinds of algorithms.
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Wireless CPU® Q24 Series Interfaces When the operating system is not activated (VBATT< 3V2), the battery charging procedure remains possible by hardware control as long as the charger is plugged: • VBATT<2V8: the battery is charged through a trickle current • 2V8
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Wireless CPU® Q24 Series Interfaces 3.14.3 Ni-Cd / Ni-Mh Charging Algorithm During the charging process of a Ni-Cd and Ni-Mh battery, it is required to tune software parameters in the Wireless CPU® operating system: AT+WBCM=, , , , , , , (See the AT command Interface Guide [4]). Caution: The parameters need to be tuned according to the battery specifications.
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Wireless CPU® Q24 Series Interfaces Ni-Cd / Ni-Mh charging process Charger connected: CHG_IN =VBATT+0.
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Wireless CPU® Q24 Series Interfaces 3.14.
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Wireless CPU® Q24 Series Interfaces Li-Ion battery and tunable parameters Parameters Default value Min Max Unit T1 90 70 90 min T2 90 60 90 min T3 5000 100 10000 ms BattLevelMin 3400 3400 3800 mV BattLevelMax 4200 4000 5000 mV DedicatedVoltStart 4000 4000 4199 mV ChargingCurrent 500 500 800 mA MaxVoltPulse 4608 4200 4608 mV TdeltaTemp 3 1 5 mm Max_Battery_Temp_Volt 2171 (≈3ûC) 1816 (≈14ûC) 2256 (≈ 0ûC) mV Max_Battery_Temp_Volt 908 (≈42û) 831 (≈45ûC)
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Wireless CPU® Q24 Series Interfaces The graph below summarizes the charging process (charge and discharge). Note: A charger is connected to the CHG_IN pin of Wireless CPU®. Figure 9: Li-Ion full-charging waveform ©Confidential Page: 52 / 83 This document is the sole and exclusive property of WAVECOM. Not to be distributed or divulged without prior written agreement.
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Wireless CPU® Q24 Series Interfaces 3.15 ON / ~OFF 3.15.1 General Description This input is used to power ON or OFF the Wireless CPU®. To power-ON, a high level signal must be provided on the ON/~OFF pin of the Wireless CPU®. To power-OFF, the ON/~OFF signal must be set to low and the AT command “AT+CPOF” must be sent to the Wireless CPU®. .
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Wireless CPU® Q24 Series Interfaces 3.15.2 Operating Sequences 3.15.2.1 Power-ON Once the Wireless CPU® is supplied, the ON/~OFF signal must be asserted high during a delay of Ton-hold (Hold delay on the ON/~OFF signal) to power-ON. After this delay, once the firmware has completed its power-up sequence, an internal logic maintains the Wireless CPU® in power-ON condition.
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Wireless CPU® Q24 Series Interfaces The recommended way to de-assert the ON/~OFF signal is to use either an AT command or WIND indicators: the application must detect the end of the power-up initialization and de-assert ON/~OFF afterwards. • Send an “AT” command and wait for the “OK” answer: once the initialization is complete the AT interface answers « OK » to “AT” message1.
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Wireless CPU® Q24 Series Interfaces 3. When using a battery as power source, it is not recommended to let this signal high: If the battery voltage is too low and the ON/~OFF signal at low level, an internal mechanism switches OFF the Wireless CPU®. This automatic process prevents the battery to be over discharged and optimize its life span. 4. During the power-ON sequence, an internal reset is automatically performed by the Wireless CPU® for 42 ms (typical).
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Wireless CPU® Q24 Series Interfaces 3.16 BOOT (optional) This input may be used to download software to the Flash memory of the Wireless CPU®. For applications based on AT commands, this is a backup download procedure (refer to document [6] Customer Design Guidelines). The internal BOOT procedure starts when this pin is low during Wireless CPU® reset. Caution: • This BOOT pin must be left open for normal use or X-modem download. • The nominal firmware download procedure uses the X-modem.
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Wireless CPU® Q24 Series Interfaces o Otherwise: - Wireless CPU® reset procedure may not perform correctly - Wireless CPU® may be damaged • If an external hardware reset happens with the ON/~OFF signal set to low, the Wireless CPU® powers OFF • If an external hardware reset happens with ON/~OFF signal set to high, the Wireless CPU® re-starts Equivalent circuit Q24 Series Power ON Reset GND 4K7 2V8 ~RST 4K7 10nF GND VT+ System VT- Reset 10nF GND Pin description Signal Pin number I/O I/
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Wireless CPU® Q24 Series Interfaces If used (as an emergency reset), it must be driven either by an open collector or an ~RST open drain output: External reset GND Figure 12: RST pin connection For the implementation of the reset interface, refer to Customer Design Guidelines [6]. 3.17.2 Reset Sequence To activate the "emergency "reset sequence, the ~RST signal must be set to low for 500 µs minimum. As soon as the reset is completed, the AT interface answers "OK" to the application.
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Wireless CPU® Q24 Series Interfaces Pin description Signal Pin number I/O ~INTR 16 I I/O type Reset state Description CMOS (C5) Pull-up to 2V8 External Interrupt (C5): To obtain more details on I/O type, refer to the section 4.2 "I/O Circuit diagram" Electrical characteristics Parameter Min Max Unit VIL -0.5 0.7 V VIH 2.2 3.0 V The external interrupt may be used to switch OFF the Wireless CPU®.
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Wireless CPU® Q24 Series Interfaces 3.19 VCC Output This output may be used to power some external functions. This power supply is available when the Wireless CPU® is ON. Pin description Signal Pin number I/O I/O type Description VCC 40 O Supply Digital supply Operating conditions Parameter Condition Output voltage I=0 I = 100 mA Min Unit 2.86 V 2.74 Output Current 3.
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Wireless CPU® Q24 Series Interfaces Pin description Signal Pin number I/O I/O type Description VCC_RTC 56 I/O Supply RTC Back-up supply Operating conditions Parameter Condition Input voltage Min Typ Max Unit 2.75 V 3 10 µA 2 VCC_RTC=2.5 V Input current VDD=3.6V Output voltage VDD=3.6V, Iout=0.5mA 2.65 2.7 2.75 V Output current VDD=3.6, Vout=2.25V 0.4 1 2 mA 3.21 RF Interface The impedance is 50Ω nominal and the DC impedance is 0Ω. 3.21.
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Wireless CPU® Q24 Series Interfaces in the frequency bands used for GSM 850/900MHz and 1800/1900MHz. • 0.5dB may be considered as a maximum value for loss between the Wireless CPU® and an external connector. • In order to maintain the RoHS status of the Wireless CPU®, Wavecom recommends that lead-free solder-wire and flux be used for Wireless CPU® assembly on the motherboard and RF cable, assembly on the Wireless CPU®. Example: • Solder-Wire: Kester 245 Cored 58 (Sn96.5Ag3Cu0.5) • Flux: Kester 952-D6 3.
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Wireless CPU® Q24 Series Interfaces 3.21.3 Antenna Specifications The antenna must fulfill the following requirements, as specified in the table below: • The optimum operating frequency depends on the application.
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Wireless CPU® Q24 Series Technical Specifications 4 Technical Specifications 4.
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Wireless CPU® Q24 Series Technical Specifications Pin Name I/O I/O type Reset state Description Dealing with unused pins CMOS (C4) Pull-down to 0V General Purpose Input or Transmit serial data (UART2) Not connected I/O CMOS/ CMOS 1X Pull-down to 0V Keyboard Row Not connected 20 GPO2 or CT104/RXD2 O CMOS 3X (C1) or CMOS 1X (C1) 2V8 General Purpose Output or Receive serial data (UART2) Not connected 21 ROW4 I/O CMOS/ CMOS 1X Pull-down to 0V Keyboard Row Not connected 22 GPO1 O CM
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Wireless CPU® Q24 Series Technical Specifications Pin Name 35 36 37 38 GPIO5 or CT105/RTS2 CT107/DSR1 CT106/CTS1 BAT_TEMP I/O I/O type Reset state Description Dealing with unused pins I/O I CMOS/CMOS 2X (C1) or CMOS High impedance General Purpose I/O or Clear To Send (UART2) Not connected O CMOS 1X (C3) 2V8 Data Set Ready (UART1) Not connected O CMOS 1X (C1) High impedance Clear To Send (UART1) Test point (Download purposes) Analog High impedance ADC input for battery temperature m
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Wireless CPU® Q24 Series Technical Specifications Pin Name I/O I/O type Reset state Description Dealing with unused pins 54 GPIO2 or CT125 / RI1 I/O O CMOS/CMOS 2X (C1) or CMOS 2X (C1) High impedance General Purpose I/O or Ring Indicator (UART1) Not connected 55 +VBATT I Supply - Battery Input Must be used 56 VCC_RTC I/O Supply 2V8 RTC back-up supply Not connected 57 +VBATT I Supply - Battery Input Must be used 58 +VBATT I Supply - Battery Input Must be used 59 +VBATT
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Wireless CPU® Q24 Series Technical Specifications 4.2 I/O Circuit Diagram The following drawings show the internal interface of the Wireless CPU® Q24 Series. The type indication per interface can be found in the previous chapters.
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Wireless CPU® Q24 Series Environmental Specifications 5 Environmental Specifications The Wireless CPU® Q24 Classic and Q24 Plus are compliant with the following operating classes: Condition Operating / Class A Storage Temperature range -20°C to +55°C for GSM 850 / 900 -10°C to +55°C for GSM 1800/1900 -40°C to +85°C The Wireless CPU® Q24 Automotive and Q24 Extended are compliant with the following operating classes: Conditions Operating / Class A Temperature range -20°C to +55°Cfor GSM 850 / 900 -10°C to
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Wireless CPU® Q24 Series Environmental Specifications 5.1 Environmental Qualifications For the Wireless CPU® Q24 Classic, Q24 Plus, and environmental qualifications are defined in the table below: Q24 Extended, applied ENVIRONMENTAL CLASSES TYPE OF TEST STANDARDS STORAGE Class 1.2 TRANSPORTATION Class 2.3 Cold IEC 68-2.1 Ab test -25° C 72 h -40° C 72 h -20° C (GSM900) -10° C (GSM1800/1900) 16 h 16h Dry heat IEC 68-2.
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Wireless CPU® Q24 Series Environmental Specifications For the Wireless CPU® Q24 Automotive, environmental qualification applied is defined in table below: Test Designation Standards Definition / Severities Temperature: +85°C Duration: 504 h Storage temperature: -40±2°C Resistance to cold test IEC 60068-2-30 Db Storage time: 72 h Temperature: +70 ±2°C Cooking Test Duration: 100 days Storage temperature: +40±2°C Damp heat test IEC 60068-2-3 Storage humidity: 95±3% Storage time: 21 days Upper temperature: +
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Wireless CPU® Q24 Series Environmental Specifications 5.2 Reflow Soldering The Wireless CPU® Q24 Series do not support any reflow soldering. 5.3 Conformance with ATEX 94/9/CE Directive To evaluate the conformity of the final product with ATEX 94/9/CE directive the following datas must be taken into account: • • Sum of all capacitors Sum of all inductances : 93µF : 11µH 5.4 Mechanical Specifications 5.4.1 Physical Characteristics The Wireless CPU® Q24NG sub-series have a complete self-contained shield.
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Wireless CPU® Q24 Series Connector and Peripheral Device References 6 Connector and Peripheral Device References 6.1 General Purpose Connector Data Sheet The GPC is a 60-pin connector with 0.5mm pitch from the KYOCERA / AVX group, with the following reference: • 14 5087 060 930 861 or 19 5087 060 930 861. The matting connector has the following reference: • 24 5087 060 X00 861. The stacking height is 3.0 mm. More information is available from http://www.avxcorp.com. 6.
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Wireless CPU® Q24 Series Connector and Peripheral Device References 6.5 Antenna Cable The following cable reference has been certified for mounting on the Wireless CPU® Q24 Series: • RG178 6.6 RF board-to-board Connector The supplier for the IMP connector is Radiall (http://www.radiall.com) with the following references: • R107 064 900. • R107 064 920. The supplier for the MMS connector is Radiall (http://www.radiall.com) 6.
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Wireless CPU® Q24 Series Appendix 7 Appendix 7.1 Standards and Recommendations GSM ETSI, 3GPP, GCF, and NAPRD.03 recommendations for Phase II. Specification Reference 3GPP TS 45.005 v5.5.0 (2002-08) Release 5 GSM 02.07 V8.0.0 (1999-07) GSM 02.60 V8.1.0 (1999-07) GSM 03.60 V7.9.0 (2002-09) 3GPP TS 43.064 V5.0.0 (2002-04) 3GPP TS 03.22 V8.7.0 (2002-08) 3GPP TS 03.40 V7.5.0 (2001-12) 3GPP TS 03.41 V7.4.0 (2000-09) ETSI EN 300 903 V8.1.1 (2000-11) 3GPP TS 04.06 V8.2.
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Wireless CPU® Q24 Series Appendix Specification Reference 3GPP TS 04.08 V7.18.0 (2002-09) 3GPP TS 04.10 V7.1.0 (2001-12) 3GPP TS 04.11 V7.1.0 (2000-09) 3GPP TS 45.005 v5.5.0 (2002-08) 3GPP TS 45.008 V5.8.0 (2002-08) 3GPP TS 45.010 V5.1.0 (2002-08) 3GPP TS 46.010 V5.0.0 (2002-06) 3GPP TS 46.011 V5.0.0 (2002-06) 3GPP TS 46.012 V5.0.0 (2002-06) 3GPP TS 46.031 V5.0.0 (2002-06) 3GPP TS 46.032 V5.0.0 (2002-06) TS 100 913V8.0.
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Wireless CPU® Q24 Series Appendix Specification Reference GSM 09.07 V8.0.0 (1999-08) 3GPP TS 51.010-1 v7.3.1 (2006-10) 3GPP TS 51.011 V5.0.0 (2001-12) ETS 300 641 (1998-03) GCF-CC V3.23.1 (2006-07) NAPRD03 v3.8.1 (2006-08) Title Digital cellular telecommunications system (Phase 2+); General requirements on inter-working between the Public Land Mobile Network (PLMN) and the Integrated Services Digital Network (ISDN) or Public Switched Telephone Network (PSTN) (GSM 09.07 version 8.0.
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Wireless CPU® Q24 Series Appendix The license module will have a FCC ID label on the module itself. The FCC ID label must be visible through a window or it must be visible when an access panel, door or cover is easily removed.
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Wireless CPU® Q24 Series Appendix 7.2 Safety Recommendations (for Information only) IMPORTANT FOR THE EFFICIENT AND SAFE OPERATION OF YOUR GSM APPLICATION BASED ON Wireless CPU® Q24 Series PLEASE READ THIS INFORMATION CAREFULLY 7.2.1 RF safety 7.2.1.1 General Your GSM terminal is based on the GSM standard for cellular technology. The GSM standard is spread all over the world. It covers Europe, Asia and some parts of America and Africa. This is the most used telecommunication standard.
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Wireless CPU® Q24 Series Appendix 7.2.1.4 Antenna Care and Replacement • Do not use the GSM terminal with a damaged antenna. If a damaged antenna comes into contact with the skin, a minor burn may result. Replace the damaged antenna immediately. You may repair antenna to yourself by following the instruction manual provided to you. If so, use only a manufacturer-approved antenna. Otherwise, have your antenna repaired by a qualified technician.
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Wireless CPU® Q24 Series Appendix To prevent possible interference with aircraft systems, Federal Aviation Administration (FAA) regulations require you should have prior permission from crew members, to use your terminal while the aircraft is on the ground. In order to prevent interference with cellular systems, local RF regulations prohibit using your modem while airborne. 7.2.2.6 Children Do not allow children to play with your GSM terminal. It is not a toy.
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