Product data

UJA1167 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet Rev. 2 — 18 April 2014 9 of 60
NXP Semiconductors
UJA1167
Mini high-speed CAN system basis chip with Standby/Sleep modes &
watchdog
power-on detection threshold V
th(det)pon
(triggering an initialization process) and switches
to Reset mode after t
startup
. In Off mode, the CAN pins disengage from the bus (zero load;
high-ohmic).
6.1.1.6 Overtemp mode
Overtemp mode is provided to prevent the UJA1167 being damaged by excessive
temperatures. The UJA1167 switches immediately to Overtemp mode from any mode
(other than Off mode or Sleep mode) when the global chip temperature rises above the
overtemperature protection activation threshold, T
th(act)otp
.
To help prevent the loss of data due to overheating, the UJA1167 issues a warning when
the IC temperature rises above the overtemperature warning threshold (T
th(warn)otp
). When
this happens, status bit OTWS is set and an overtemperature warning event is captured
(OTW = 1), if enabled (OTWE = 1).
In Overtemp mode, the CAN transmitter and receiver are disabled and the CAN pins are
in a high-ohmic state. No wake-up event will be detected, but a pending wake-up will still
be signalled by a LOW level on pin RXD, which will persist after the overtemperature
event has been cleared. V1 is off and pin RSTN is driven LOW after t
d(uvd)V1
. In the
UJA1167TK/VX, VEXT is off. In the UJA1167TK, INH remains unchanged when the SBC
enters Overtemp mode.
The UJA1167 exits Overtemp mode:
• and switches to Reset mode if the chip temperature falls below the overtemperature
protection release threshold, T
th(rel)otp
• if the device is forced to switch to Off mode (V
BAT
< V
th(det)poff
)
6.1.1.7 Forced Normal mode
Forced Normal mode simplifies SBC testing and is useful for initial prototyping and failure
detection, as well as first flashing of the microcontroller. The watchdog is disabled in
Forced Normal mode. The low-drop voltage regulator (V1) is active, VEXT/INH is enabled
and the CAN transceiver is active.
Bit FNMC is factory preset to 1, so the UJA1167 initially boots up in Forced Normal mode
(see Table 8
). This allows a newly installed device to be run in Normal mode without a
watchdog. So the microcontroller can be flashed via the CAN bus in the knowledge that a
watchdog timer overflow will not trigger a system reset.
The register containing bit FNMC (address 74h) is stored in non-volatile memory (see
Section 6.11
). So once bit FNMC is programmed to 0, the SBC will no longer boot up in
Forced Normal mode, allowing the watchdog to be enabled.
Even in Forced Normal mode, a reset event (e.g. an external reset or a V1 undervoltage)
will trigger a transition to Reset mode with normal Reset mode behavior (except that the
transmitter remains active if there is no V1 undervoltage). However, when the UJA1167
exits Reset mode, it will return to Forced Normal mode instead of switching to Standby
mode.
In Forced Normal mode, only the Main status register, the Watchdog status register, the
Identification register and registers stored in non-volatile memory can be read. The
non-volatile memory area is fully accessible for writing as long as the UJA1167 is in the
factory preset state (for details see Section 6.11
).