Product data

UJA1167 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet Rev. 2 — 18 April 2014 8 of 60
NXP Semiconductors
UJA1167
Mini high-speed CAN system basis chip with Standby/Sleep modes &
watchdog
Any enabled regular wake-up via CAN or WAKE or any diagnostic wake-up event will
cause the UJA1167 to wake up from Sleep mode. The behavior of INH/VEXT is
determined by the SPI settings. The SPI and the watchdog are disabled. Autonomous bus
biasing is active.
Sleep mode can be selected from Normal or Standby mode via an SPI command
(MC = 001). The UJA1167 will switch to Sleep mode on receipt of this command, provided
there are no pending wake-up events and at least one regular wake-up source is enabled.
Any attempt to enter Sleep mode while one of these conditions has not been met will
cause the UJA1167 to switch to Reset mode and set the reset source status bits (RSS) to
10100 (‘illegal Sleep mode command received’; see Table 5
).
Since V1 is off in Sleep mode, the only way the SBC can exit Sleep mode is via a wake-up
event (see Section 6.10
).
Sleep mode can be permanently disabled in applications where, for safety reasons, the
supply voltage to the host controller must never be cut off. Sleep mode is permanently
disabled by setting the Sleep control bit (SLPC) in the SBC configuration register (see
Table 8
) to 1. This register is located in the non-volatile memory area of the device. When
SLPC = 1, a Sleep mode SPI command (MC = 001) triggers an SPI failure event instead
of a transition to Sleep mode.
6.1.1.4 Reset mode
Reset mode is the reset execution state of the SBC. This mode ensures that pin RSTN is
pulled down for a defined time to allow the microcontroller to start up in a controlled
manner.
The transceiver is unable to transmit or receive data in Reset mode. The behavior of
INH/VEXT is determined by the settings of bits VEXTC and VEXTSUC (see Section 6.6
).
The SPI is inactive; the watchdog is disabled; V1 and overtemperature detection are
active.
The UJA1167 switches to Reset mode from any mode in response to a reset event (see
Table 5
for a list of reset sources).
The UJA1167 exits Reset mode:
• and switches to Standby mode if pin RSTN is released HIGH
• and switches to Forced Normal mode if bit FNMC = 1
• if the SBC is forced into Off or Overtemp mode
If a V1 undervoltage event forced the transition to Reset mode, the UJA1167 will remain in
Reset mode until the voltage on pin V1 has recovered.
After the UJA1167 exits Reset mode (positive edge on RSTN), an SPI read/write access
must not be attempted for at least t
to(SPI)
. Any earlier access may be ignored (without
generating an SPI failure event).
6.1.1.5 Off mode
The UJA1167 switches to Off mode when the battery is first connected or from any mode
when V
BAT
< V
th(det)poff
. Only power-on detection is enabled; all other modules are
inactive. The UJA1167 starts to boot up when the battery voltage rises above the