Product data

UJA1167 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet Rev. 2 — 18 April 2014 48 of 60
NXP Semiconductors
UJA1167
Mini high-speed CAN system basis chip with Standby/Sleep modes &
watchdog
Fig 11. Loop delay symmetry timing diagram
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ELW7;'
[W
ELW7;'
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ELW5;'
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DDD
7;'
5;'
Fig 12. SPI timing diagram
DDD
6&61
6&.
6',
6'2
;
; ;
06% /6%
06% /6%
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IORDWLQJ
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K'
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VX'
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FON/
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FON+
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63,/($'
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F\FON
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63,/$*
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:+6