Product data

UJA1167 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet Rev. 2 — 18 April 2014 47 of 60
NXP Semiconductors
UJA1167
Mini high-speed CAN system basis chip with Standby/Sleep modes &
watchdog
[1] Guaranteed by design.
[2] See Figure 11
.
[3] A system reset will be performed if the watchdog is in Window mode and is triggered less than t
trig(wd)1
after the start of the watchdog
period (or in the first half of the watchdog period).
[4] The nominal watchdog period is programmed via the NWP control bits.
[5] The watchdog will be reset if it is in window mode and is triggered at least t
trig(wd)1
, but not more than t
trig(wd)2
, after the start of the
watchdog period (or in the second half of the watchdog period). A system reset will be performed if the watchdog is triggered more than
t
trig(wd)2
after the start of the watchdog period (watchdog overflows).
Pin WAKE
t
wake
wake-up time 50 - - s
MTP non-volatile memory
t
d(MTPNV)
MTPNV delay time before factory presets are
restored
0.9 - 1.1 ms
Table 47. Dynamic characteristics …continued
T
vj
=  40  C to +150  C; V
BAT
= 3 V to 28 V; R
(CANH-CANL)
= 60  ; all voltages are defined with respect to ground; positive
currents flow into the IC; typical values are given at V
BAT
= 13 V; unless otherwise specified.
Symbol Parameter Conditions Min Typ Max Unit
Fig 10. CAN transceiver timing diagram
&$
1+
&$
1/
W
G7;'EXVGRP
7;
'
9
2GLIEXV
5;
'
+,*+
+,*
+
/2:
/2:
GRP
LQDQW
UHFH
VVLYH
9
9
W
GEXVGRP5;'
W
G7;'EXVUHF
W
GEXVUHF5;'
W
G7;'5;'
W
G7;'5;'
DDD